{"id":248664,"date":"2025-06-12T19:39:18","date_gmt":"2025-06-12T17:39:18","guid":{"rendered":"https:\/\/www.hwcooling.net\/?p=248664\/"},"modified":"2025-06-12T19:39:18","modified_gmt":"2025-06-12T17:39:18","slug":"tsmcs-1-6nm-chips-will-be-unprecedentedly-expensive","status":"publish","type":"post","link":"https:\/\/www.hwcooling.net\/en\/tsmcs-1-6nm-chips-will-be-unprecedentedly-expensive\/","title":{"rendered":"TSMC\u2019s 1.6nm chips will be unprecedentedly expensive"},"content":{"rendered":"

For a long time, Moore\u2019s Law meant new technologies provided more transistors for the same or lower cost, as more could fit onto a chip of the same size. But in the last decade, production costs have been rising, transistors are no longer getting cheaper, and same-sized chips are costing more. And after the 2nm process, things will escalate dramatically \u2013 a single wafer will cost nearly ten times more than it did ten years ago.<\/p>\n

Taiwanese site China Times published information on pricing for TSMC\u2019s upcoming manufacturing nodes last week. The pricing is something the company doesn\u2019t advertise directly, and exact numbers are part of individual offers and negotiations, as is typical in the space of B2B services and products. Nevertheless, it’s possible to estimate a ballpark figure for a fabricated silicon wafer (which is a 300mm-diameter disc from which chips are made), around which contractual prices will likely revolve.<\/p>\n

Wafer pricing is a problem<\/h3>\n

The issue with modern manufacturing processes is that the wafer itself remains the same size (meaning the number of final dies made from it stays similar for a given chip area), but its price keeps going up. While manufacturing a wafer used to cost under $5,000 ten years ago, prices have been steadily rising since the advent of FinFET nodes and later the EUV technology. And to make matters worse, these new processes no longer deliver the same transistor density improvements they provided in the past. According to China Times, the cost of a wafer on the 2nm N2 process is around $30,000, while for the 3nm node, it\u2019s estimated between 18,000 USD and 20,000 USD.<\/p>\n

\"Proces<\/a>
TSMC A16 process node (Author: TSMC, via: Tom’s Hardware)<\/figcaption><\/figure>\n

The price for the next-generation 1.6nm process (A16 technology) is expected to jump by another 50%. TSMC is reportedly considering charging up to 45,000 USD per wafer. If CPU and GPU manufacturers produce chips of the same die size, their silicon costs would increase by the same proportion. This would likely affect end-user prices, although the final product includes many components, so we might not feel the full 50% increase directly.<\/p>\n

This trend of rising costs in cutting-edge technologies may lead to broader use of chiplet architectures, with the most advanced process nodes being used only for smaller portions of a CPU, SoC, or GPU, with other parts increasingly being disaggregated into silicon built with older and cheaper process nodes.<\/p>\n

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  • Read more: <\/strong>2nm, 1,6nm and latest 1,4nm process details: What does TSMC have in store?<\/strong><\/a><\/li>\n<\/ul>\n

    Price increases have accelerated sharply<\/h3>\n

    To understand how dramatically chip manufacturing costs have risen, consider estimates published by Tom\u2019s Hardware. Until about a decade ago, prices remained relatively low, making the latest nodes fairly accessible. In 2004, a wafer produced on TSMC\u2019s 90nm process cost 2,000 USD. By 2014, a 28nm wafer cost 3,000 USD \u2013 but this increase occurred gradually across several generations and “half-node” steps (80nm, 65nm, 55nm, 40nm generations).<\/p>\n

    In 2016, the 10nm process cost 6,000 USD. Two years later, 7nm wafers cost $10,000. Another two years on, 5nm wafers reached 16,000 USD, and the current 3nm process has pushed that to 18,000\u201320,000 USD per wafer. We now face a projected 50% markup every two years, which is roughly the cadence of new process generation introductions.<\/p>\n

    \"Wafer<\/a>
    A silicon wafer. Individual chip dies are produced side by side on a circular silicon disc 300mm in diameter (older fabs still use 150mm or 200mm wafers), and eventually sliced apart (Source: Intel)<\/figcaption><\/figure>\n

    Despite the skyrocketing costs, competitive pressure still continues to push chipmakers toward adopting the most advanced nodes for now (and they\u2019ll probably have to pass those costs on to end users). Besides Apple, MediaTek will also produce chips on the 2nm node, and AMD has confirmed its plans as well.<\/p>\n

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    • Read more: AMD boasts the first 2nm processor \u2013 First \u201cHPC\u201d one, that is<\/a><\/strong><\/li>\n<\/ul>\n

      Fujitsu is reportedly preparing its own chips on this technology (likely for expensive server and HPC hardware, not consumer products). Qualcomm\u2019s new Snapdragon 8 Elite will also be made on this node, as will proprietary chips from companies like Microsoft (the Maia 300 AI accelerator), Google (8th-gen TPU), and Amazon (Trainium 4). TSMC is reportedly aiming to offer production volume of 30,000 wafers per month on the 2nm process by the end of the year.<\/p>\n

      It\u2019s not just the per-chip manufacturing cost that\u2019s becoming a luxury \u2013 fixed costs for developing and ramping up production of a chip are also rising. According to China Times, the full process of developing and preparing a 2nm chip could cost up to $725 million. That\u2019s money that must be recovered from product margins \u2013 and it is yet another factor that will contribute to raised prices of products that we as consumers ultimately pay.<\/p>\n

      Sources: China Times<\/a>, Tom\u2019s Hardware<\/a><\/em><\/p>\n

      English translation and edit by Jozef Dud\u00e1\u0161<\/em><\/p>\n