{"id":255178,"date":"2025-07-28T21:56:08","date_gmt":"2025-07-28T19:56:08","guid":{"rendered":"https:\/\/www.hwcooling.net\/?p=255178\/"},"modified":"2025-07-28T21:56:08","modified_gmt":"2025-07-28T19:56:08","slug":"bllc-in-nova-lake-cpus-intels-answer-to-amd-x3d-processors","status":"publish","type":"post","link":"https:\/\/www.hwcooling.net\/en\/bllc-in-nova-lake-cpus-intels-answer-to-amd-x3d-processors\/","title":{"rendered":"BLLC in Nova Lake CPUs: Intel\u2019s Answer to AMD X3D processors"},"content":{"rendered":"

Gaming used to be a strength of Intel CPUs, but that changed with AMD\u2019s \u201cX3D\u201d chips featuring 3D V-Cache. First the Ryzen 7 7800X3D<\/a>, and then last year\u2019s Ryzen 7 9800X3D<\/a>, has gained significant lead in games , while Intel\u2019s new Core Ultra 200 lineup has disappointed. But next year, Intel may have a shot at reclaiming ground\u2014it’s preparing its own version of CPUs with large L3 cache, which could bring similar benefits to 3D V-Cache.<\/p>\n

Details on these processors have now surfaced online from the leaker known as OneRaichu. As always with such leaks, take them with a grain of salt\u2014mistakes or misinformation are possible. Still, the info is intriguing.<\/p>\n

BLCC<\/h3>\n

According to OneRaichu, Intel\u2019s alternative to 3D V-Cache, referred to as BLLC (Big Last-Level Cache), will be featured in two Nova Lake desktop processor models. Both will be based on a Nova Lake variant with a single CPU chiplet\u2014one higher-end model with 8 P-Cores and 16 E-Cores, and a lower-end version with 8 P-Cores and 12 E-Cores. Essentially, they\u2019ll be the counterparts of today\u2019s Core Ultra 9 \/ Core i9 and Core Ultra 7 \/ Core i7. Nova Lake processors will also include 4 LP E-Cores in the SoC chiplet in addition, but those likely won\u2019t play a significant role in gaming.<\/p>\n

Earlier reports suggest that the BLLC (also written as bLLC in some references) cache could offer a capacity of 144 MB<\/strong>. It\u2019s still unclear whether this is the total L3 cache of the CPU or if the 144 MB will be added to the L3 cache already present in the CPU (for example, the current Core Ultra 9 285K<\/a> already has 36 MB in total). The TDP for BLLC CPUs is reportedly 125 W. As usual, the maximum turbo power will be higher.<\/p>\n

It appears that BLLC won\u2019t be available in CPUs with multiple compute chiplets. Leaks suggest Nova Lake will also come in dual-chiplet versions<\/a>, supporting up to 52 cores (16 P-Cores, 32 E-Cores, and 4 LP E-Cores in the SoC chiplet). However, these will not be available as BLLC gaming variants.<\/p>\n

That might be due to the way Intel has implemented BLLC. Based on leaks so far, it\u2019s not a separate SRAM chiplet connected via 3D stacking on top of or beneath the CPU chiplet. Instead, it might use \u201c2.5D\u201d packaging, where the cache chiplet is placed alongside the CPU chiplet and connected via a silicon bridge or interposer. Alternatively, BLLC could be integrated directly into the CPU chiplet itself\u2014significantly increasing its size. That would require a separate mask and tape-out.<\/p>\n

A monolithic large chiplet could deliver excellent performance and potentially avoid the limitations on clock speeds due to voltage sensitivity, a known drawback of AMD’s X3D processors. With 2.5D packaging, such voltage or clock speed limits could also happen in theory but are not guaranteed to. Either way, both designs take up more space, and that may be the reason why BLLC can\u2019t be combined with dual-chiplet CPUs.<\/p>\n

\"Dva<\/a>
Two CPU chiplets in an AMD Ryzen 7000 (Raphael) processor for socket AM5, without the metal IHS (Author: AMD)<\/figcaption><\/figure>\n

Will BLLC be as good as \u201cX3D\u201d?<\/h3>\n

Just having a large cache doesn\u2019t guarantee great results, so it\u2019s still unclear whether Intel will be able to match the gaming performance of AMD\u2019s X3D CPUs\u2014it will depend on the cache’s performance characteristics like bandwidth and latency. That said, the potential for strong gaming performance is there.<\/p>\n

Current Arrow Lake CPUs seem to underperform in games for two main reasons. First is the increased memory latency, caused by the memory controller not being on the same chiplet as the CPU cores. They communicate via a \u201cD2D\u201d interface, which apparently suffers from poor performance. A large cache could help significantly here, as its main advantage is shielding the CPU from the negative effects of memory latency (and bandwidth), by handling a large portion of memory accesses itself. X3D Ryzen chips are known to be far less sensitive to slower RAM in games than their non-X3D counterparts.<\/p>\n

The second factor is that Arrow Lake has relatively poor L3 cache and ring bus performance. This is likely another side effect of the chiplet design and the performance penalties tied to D2D links. These issues could diminish the benefits of a larger L3 cache\u2014whether it\u2019s part of the main CPU chiplet or a separate SRAM block in another chiplet. In recent years, Intel\u2019s L3 cache has generally lagged behind AMD\u2019s in both latency and bandwidth, and it will need architectural improvements to close that gap. Whether Nova Lake will deliver on that front remains to be seen.<\/p>\n

Nova Lake CPUs are expected in the second half of 2026, debuting with the new LGA 1954 socket<\/a>. They may launch as the Core Ultra 400 series (we assume that the Core Ultra 300 designation will be used by this year\u2019s Panther Lake generation<\/a>, which will likely only exist for laptops, with the desktop 300 series skipped entirely).<\/p>\n

According to leakers, Intel is expected to first release versions with a single CPU chiplet, while dual-chiplet versions with up to 52 cores will follow a quarter later (possibly in Q1 2027 instead of Q4 2026). The gaming CPUs with BLLC\u2014being based on the single-chiplet design\u2014could arrive in the initial wave.<\/p>\n

Sources: OneRaichu<\/a>, Haze<\/a>, VideoCardz<\/a><\/em><\/p>\n

English translation and edit by Jozef Dud\u00e1\u0161<\/em><\/p>\n