{"id":255368,"date":"2025-08-01T21:18:18","date_gmt":"2025-08-01T19:18:18","guid":{"rendered":"https:\/\/www.hwcooling.net\/?p=255368\/"},"modified":"2025-08-01T21:18:52","modified_gmt":"2025-08-01T19:18:52","slug":"intel-reverses-course-hyper-threading-returns-to-cpus","status":"publish","type":"post","link":"https:\/\/www.hwcooling.net\/en\/intel-reverses-course-hyper-threading-returns-to-cpus\/","title":{"rendered":"Intel reverses course: Hyper-Threading returns to CPUs"},"content":{"rendered":"<p><!--nextpage-->We&#8217;ve already written about <a href=\"https:\/\/www.hwcooling.net\/en\/intel-kills-eu-fabs-chip-manufacturing-exit-after-1-4nm-node\/\">the painful measures Intel is implementing<\/a> get out of the deep red numbers it sunk into due to maintaining and building its own chip fabs (because as a &#8220;fabless&#8221; player, Intel would be profitable). Among them, however, is one unexpected development: Intel processors are set to reintroduce Hyper-Threading technology for processing multiple threads simultaneously. And this is actually quite peculiar&#8230;<!--more--><\/p>\n<p>Hyper-Threading or HT (Intel&#8217;s proprietary branding), or more generally SMT (Simultaneous Multi-Threading), is a technology where a single processor core can handle multiple threads concurrently\u2014typically two, though some <a href=\"https:\/\/www.hwcooling.net\/en\/power11-is-here-new-generation-of-ibm-risc-processors-detailed\/\">IBM Power<\/a> processors or Sparc chips in the past could manage up to eight. The rationale is that additional threads can make use of processor resources that a single thread might leave idle\u2014for instance, while waiting for memory data. This technique typically improves multi-threaded performance.<\/p>\n<p>HT had been a staple in Intel processors since the Nehalem architecture (the first &#8220;Core i&#8221; processors in 2008), though it was already tried before in the infamous Pentium 4. Last year, Intel officially abandoned it wit the launch of the Core Ultra 200 mobile processors (<a href=\"https:\/\/www.hwcooling.net\/en\/the-comeback-of-intel-next-gen-lunar-lake-mobile-cpu-introduced\/\">Lunar Lake<\/a>) and later desktop processors (<a href=\"https:\/\/www.hwcooling.net\/en\/core-ultra-200s-arrow-lake-new-intel-desktop-cpus-are-here\/\">Arrow Lake<\/a>). Their P-Cores (codenamed Lion Cove) now process only one thread. Intel claimed removing HT (SMT) would shrink die size and improve efficiency by specializing P-Cores purely for single-thread performance. We detailed this in our architecture analysis:<\/p>\n<ul>\n<li><strong>Read more: <a href=\"https:\/\/www.hwcooling.net\/en\/intels-new-p-core-lion-cove-is-the-biggest-change-since-nehalem\/\" rel=\"bookmark\">Intel\u2019s new P-Core: Lion Cove is the biggest change since Nehalem<\/a><\/strong><\/li>\n<\/ul>\n<h4 id=\"h41\">x86 revitalization<\/h4>\n<p>Now, in the same statement that announced the cancellation of European and Costa Rican fabs, Intel states it will take steps to halt and reverse its declining market share in PC and server processors\u2014literally to revitalize the &#8220;Intel x86 ecosystem.&#8221;<\/p>\n<p>Among these revitalization attempts, Lip-Bu Tan mentions reintroducing Hyper-Threading. He cites its removal as a mistake that cost Intel market share and revenue, explicitly stating it created a &#8220;competitive disadvantage&#8221; and that its return will help &#8220;close performance gaps.&#8221;<\/p>\n<blockquote><p><em>&#8230;we are reintroducing simultaneous multi-threading (SMT). Moving away from SMT put us at a competitive disadvantage. Bringing it back will help us close performance gaps.<\/em><\/p><\/blockquote>\n<p>Notably, these HT remarks (where Tan used the generic &#8220;SMT&#8221; term\u2014also employed by AMD\u2014rather than Intel&#8217;s &#8220;HT&#8221; branding, by the way) appeared in the context of Xeon server processors. But since these share P-Cores with desktop\/mobile Core\/Core Ultra chips, the statement might also apply to consumer processors\u2014though this isn&#8217;t certain. Many users would welcome HT&#8217;s return for improved multi-threading performance, as its absence drew frequent criticism (whether justified or not).<\/p>\n<figure id=\"attachment_208638\" aria-describedby=\"caption-attachment-208638\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/10\/intel-xeon-6-gnr-ap-package-1.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-208638 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/10\/intel-xeon-6-gnr-ap-package-1-1024x591.jpg\" alt=\"\" width=\"640\" height=\"369\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/10\/intel-xeon-6-gnr-ap-package-1-1024x591.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/10\/intel-xeon-6-gnr-ap-package-1-300x173.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/10\/intel-xeon-6-gnr-ap-package-1-768x443.jpg 768w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-208638\" class=\"wp-caption-text\">Xeon 6900P (Author: Intel)<\/figcaption><\/figure>\n<h3 id=\"h32\" class=\"western\">HT removal in servers?<\/h3>\n<p>The whole mention of HT\u2019s return doesn\u2019t quite hold up in one respect\u2014and that detail may be more significant than it seems. The idea that Xeon processors for servers were supposed to lose HT (SMT) is not actually something that was previously known; on the contrary no such plan had been made public so far. And when the Lion Cove core used in PC processors removed HT support, Intel engineers and representatives themselves emphasized quite publicly that this is a configurable feature of the core\u2014and they maintained that even though the versions used in Lunar Lake and Arrow Lake chips did not implement this technology, the architecture still accounts for it. Crucially, Intel representatives explicitly stated in interviews that the next generation of server processors derived from this architecture would continue to support HT (SMT).<\/p>\n<p>That next generation comprises the Xeon 7000 \u201cDiamond Rapids\u201d chips (succeeding the current <a href=\"https:\/\/www.hwcooling.net\/xeon-6900p-se-128-jadry-vrati-se-intel-na-serverovy-trun\/\">6th-gen Xeon Scalable \u201cGranite Rapids\u201d<\/a>). These don\u2019t feature the Lion Cove core directly but instead use a lightly modified derivative\u2014Cougar Cove\u2014manufactured on the 1.8\u202fnm node. Cougar Cove is also set to appear in Core Ultra 300 \u201cPanther Lake\u201d processors for PCs later this year. This core isn\u2019t a true new architecture and is expected to introduce only minor evolutionary updates, you could call it Golden Cove+.<\/p>\n<p>It seems unlikely that Intel would take such a radical step as stripping HT out entirely in this core\u2014a contrast to what it did with Lion Cove. Such a major change would more reasonably be expected with the next P-Core generation that brings a fresh architectural overhaul (what Intel once called Tock in the Tick-Tock scheme). Such shift is set to happen with Coyotte Cove, which is slated to power the next wave of desktop and laptop CPUs in 2026\u2014namely, <a href=\"http:\/\/www.hwcooling.net\/tag\/nova-lake\/\">Core Ultra 400 \u201cNova Lake\u201d<\/a>. The next generation of Xeons might be based not quite on this core but on its own tweaked evolution\u2014likely named Griffin Cove\u2014which should appear in PCs as the Core Ultra 500 \u201cRazer Lake\u201d lineup in 2027, but Griffin Cove should still be mostly similar to Coyotte Cove.<\/p>\n<p>There\u2019s a catch, though: Coyotte Cove must already be finalized at this point. Intel would have locked down the architecture some time ago\u2014Nova Lake\u2019s launch is only about a year and a half away, and the design is either undergoing or has already completed tape-out. It is entirely unrealistic to suggest that Hyper-Threading support could now (or in the few months since Lip-Bu Tan took over Intel) be added to the architecture at this stage. While it\u2019s possible in theory that Intel initially planned for the server variant derived from Coyotte Cove to ship without HT, it would only be feasible to reintroduce the feature now if the core had all along been architected with that capability to re-enable HT in mind, from the start.<\/p>\n<p>Which would put it in the same position as Lion Cove\u2014not a reversal in strategy, just a continuation of an existing design. Even in such a scenario, any late-stage decision to re-enable HT would likely delay the processor\u2019s release, unless that decision had been made well in advance (say, several months\u2014more realistically, over a year) before the tape-out stage, which itself happens 12 to 18 months prior to product launch. If HT was never intended to be part of the core, we\u2019d be looking at a delay of at least three years to change course now.<\/p>\n<h3 id=\"h33\" class=\"western\">Alternative explanation: HT for small cores?<\/h3>\n<p>The entire remark about HT might actually refer to something else. The Intel executive could have been speaking about Xeon processors built with the so-called little cores (E-Cores), which the company recently began producing\u2014namely, the Xeon 6700E and 6900E. Since E-Cores have never supported Hyper-Threading, server CPUs based on them inherently lack this functionality\u2014unlike their P-Core-based counterparts.<\/p>\n<ul>\n<li><strong>Tip: <\/strong><a href=\"https:\/\/www.hwcooling.net\/intel-uvadi-xeon-6700e-sierra-forest-svuj-prvni-3nm-procesor-se-144-e-core\/\" rel=\"bookmark\"><strong>Intel introduces Xeon 6700E, its first 3nm CPU with 144 E-Cores<\/strong><\/a><\/li>\n<\/ul>\n<p>It\u2019s possible that these chips underperformed in the market, prompting Intel to discontinue the line. The comment about having \u201cmoved away from HT\u201d in server processors might thus refer simply to back.tracking on these E-Core Xeons (even though they were only ever offered as optional alternatives to models with P-Cores and HT, not replacing them) and discontinuing them. Having found them to be a misstep, Intel could now be \u201creturning to HT\u201d in the sense that it will go back to producing only server CPUs with full-fledged P-Cores and Hyper-Threading.<\/p>\n<p>Why wouldn\u2019t Intel say this more directly? Likely because phrasing it this way makes it sound better then admitting a new product line (the E-Core Xeons) was unsuccessful and the investments were wasted, avoiding the appearance of a stark failure.<\/p>\n<h3 id=\"h34\" class=\"western\">Hyper-Threading and a unified core<\/h3>\n<p>There\u2019s another complication to the HT disappearance-and-return narrative. According to multiple sources, Intel is now aiming to end development of the CPU architecture lineage currently used in large P-Cores\u2014the entire family of \u201cCove\u201d-named cores. These cores have been designed by Intel\u2019s Israeli team in Haifa, once subject of great acclaim for rescuing Intel from the Pentium 4 era with the tremendously successful Core and Core 2. The same team then went on to produce the architectures of Sandy Bridge, Skylake, and all the following generations of Intel big cores from Sunny Cove in Ice Lake to Lion Cove in Lunar and Arrow Lake.<\/p>\n<p>But that team seems to have lost momentum lately. Their cores have not been delivering performance improvements at the pace the market demands (see the relatively small performance gain in Lion Cove), despite being incredibly complex and occupying substantial die area. AMD, by contrast, appears to be able to match\u2014or even surpass\u2014that level performance (especially considering features like AVX-512) using a much smaller footprint, even now when Intel enjoys a temporary process advantage with 3\u202fnm versus Zen 5\u2019s older 4\u202fnm node. That size disadvantage is even more glaring when compared to the compact designs of ARM cores. In other words, the Cove architecture line now seems burdened with heavy cruft from its long history, and its developers have been unable to sufficiently modernize or streamline it, which undermines its competitiveness.<\/p>\n<figure id=\"attachment_195914\" aria-describedby=\"caption-attachment-195914\" style=\"width: 1920px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Procesorov\u00e1-architektura-Intel-Lion-Cove-Prezentace-02.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-195914\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Procesorov\u00e1-architektura-Intel-Lion-Cove-Prezentace-02.png\" alt=\"\" width=\"1920\" height=\"1080\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Procesorov\u00e1-architektura-Intel-Lion-Cove-Prezentace-02.png 1920w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Procesorov\u00e1-architektura-Intel-Lion-Cove-Prezentace-02-300x169.png 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Procesorov\u00e1-architektura-Intel-Lion-Cove-Prezentace-02-768x432.png 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Procesorov\u00e1-architektura-Intel-Lion-Cove-Prezentace-02-1024x576.png 1024w\" sizes=\"auto, (max-width: 1920px) 100vw, 1920px\" \/><\/a><figcaption id=\"caption-attachment-195914\" class=\"wp-caption-text\">Hyper-Threading increases performance by 30 %, according to Intel (Author: Intel, via: ComputerBase)<\/figcaption><\/figure>\n<h4 id=\"h45\">Haifa vs. Austin<\/h4>\n<p>By contrast, Intel\u2019s little\/efficient E-Core architectures have seen explosive performance growth in recent years\u2014rapidly catching up to the performance levels of previous generations of large cores developed by the Haifa team. These E-Cores are designed by a team in Austin, Texas, and crucially: they seem capable of delivering an architecture that is power-efficient and die area-efficient. Rumor has it that Intel plans to abandon the original P-Core line and instead let the Austin team handle development of both P-Cores and E-Cores\u2014starting from the current E-Core architecture lineage. Ironically, this resembles that very same pivotal moment in 2006, when Intel dropped its troubled Pentium 4 and replaced it with the Pentium M core\u2014developed by the Israeli team\u2014which immediately catapulted Intel back ahead of then-dominant AMD.<\/p>\n<p>The plan, however, is not to eliminate the distinction between core types, but rather to fork a larger, more powerful core from the E-Core line\u2014with higher IPC and higher clock speeds \u2014 to serve as the new P-Core. This strategy is referred to as the \u201cUnified Core\u201d approach. It likely doesn\u2019t signal the end of hybrid CPUs or the P-Core\/E-Core distinction (nor does it imply large cores will disappear altogether), but rather that both core types will now stem from a shared architectural foundation. According to some reports\u2014or perhaps educated guesses\u2014this \u201cUnified Core\u201d architecture is expected to debut around 2028 to 2029. It would power CPUs following after Razer Lake (Core Ultra 500) and could potentially be designated Core Ultra 600 (a possible codename has also emerged: \u201cTitan Lake.\u201d<\/p>\n<p>There\u2019s a catch, though: E-Cores today do not support HT, and this technology has never been part of their architecture\u2014with the exception of the original in-order Atom \u201cBonnell\u201d processors, which aren\u2019t closely related to the newer out-of-order \u201cMont\u201d core family. Based on this, it appears that the original Unified Core design perhaps didn\u2019t include Hyper-Threading at all. Lip-Bu Tan may now be referring to a decision to retroactively add HT to the Unified Core architecture\u2014either to the P-Core variant only, or potentially even to both P- and E-Core derivatives.<\/p>\n<p>A more pessimistic scenario would be that\u2014due to the lack of HT\u2014Intel has abandoned the plan to transition to the new unified architecture altogether. Instead, the company may choose to let the Israeli team continue refining the increasingly inefficient \u201cCove\u201d big cores, despite their disproportionately large die footprint. That would be an unfortunate decision, since smaller cores make it easier to fit more of them on a chip\u2014that itself can offset the lack of HT by sheer quantity of cores. At present, the CPU team in Austin seems significantly more capable, and it would likely benefit Intel to move forward with adopting their unified design\u2014so hopefully, Lip-Bu Tan doesn\u2019t make that kind of mistake.<\/p>\n<h3 id=\"h36\" class=\"western\">What it actually meant remains to be seen\u2026<\/h3>\n<p>At this point, all we can do is wait for more information to clarify what this announcement really signals about the turmoil and internal shifts at Intel. Hopefully it leads to welcome\u2014rather than unwelcome\u2014surprises.<\/p>\n<p>It\u2019s also possible that the reintroduction of HT isn\u2019t a major course correction by the new leadership, but simply a case of \u201cwagging the dog\u201d\u2014much ado about nothing. Lip-Bu Tan may have just needed a clear, digestible example of his actions to show investors, who likely lack deep intuition about how processor development and the surrounding business ecosystem actually work. Hyper-Threading makes for a convenient illustration: it shows the company is making changes, correcting past missteps (which implies future progress), and responding to market demands. Even if, in reality, the overall strategy remains unchanged.<\/p>\n<p>The truth is, Intel\u2019s \u201ccompetitive disadvantage\u201d seen today isn\u2019t simply caused by the absence of HT\u2014and bringing it back alone won\u2019t fix the situation (though it may help improve performance to some degree). But much like voters in democratic countries, stock investors tend to respond to simple narratives and promises of easy solutions. They don\u2019t always recognize that the underlying problems are far more complex\u2014and that magical simple fixes able to resolve them usually don&#8217;t exist.<\/p>\n<p><em>Source: <a href=\"https:\/\/newsroom.intel.com\/corporate\/lip-bu-tan-steps-in-the-right-direction\">Intel<\/a><\/em><\/p>\n<p style=\"text-align: right;\"><em>English translation and edit by Jozef Dud\u00e1\u0161<\/em><\/p>\n<p><script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script>\n<!-- responsive -->\n<ins class=\"adsbygoogle\"\n     style=\"display:block;background-color:transparent\"\n     data-ad-client=\"ca-pub-8150419924824893\"\n     data-ad-slot=\"6522017574\"\n     data-ad-format=\"auto\"><\/ins>\n<script>\n(adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n\u2800<\/p>\n","protected":false},"excerpt":{"rendered":"<p>We&#8217;ve already written about the painful measures Intel is implementing get out of the deep red numbers it sunk into due to maintaining and building its own chip fabs (because as a &#8220;fabless&#8221; player, Intel would be profitable). Among them, however, is one unexpected development: Intel processors are set to reintroduce Hyper-Threading technology for processing [&hellip;]<\/p>\n","protected":false},"author":26,"featured_media":89031,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[542,18],"tags":[1093,27,232,138,136,187],"class_list":["post-255368","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-processors","category-news","tag-architecture","tag-cpu-en","tag-intel-en","tag-servers","tag-servery-en","tag-xeon-en"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v24.9 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Intel reverses course: Hyper-Threading returns to CPUs - HWCooling.net<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.hwcooling.net\/en\/intel-reverses-course-hyper-threading-returns-to-cpus\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Intel reverses course: Hyper-Threading returns to CPUs - HWCooling.net\" \/>\n<meta property=\"og:description\" content=\"We&#8217;ve already written about the painful measures Intel is implementing get out of the deep red numbers it sunk into due to maintaining and building its own chip fabs (because as a &#8220;fabless&#8221; player, Intel would be profitable). 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