Chip and memory controller development is already underway. All three major DRAM manufacturers\u2014SK Hynix, Samsung, and Micron\u2014have working prototypes in the lab, with testing and validation currently ongoing.<\/p>\n
CPU manufacturers, including Intel and AMD, are participating in early validation. However, processors capable of supporting DDR6 won\u2019t begin integrated testing until 2026, as they\u2019re still in development. For now, testing is likely taking place via FPGAs. Since there’s always a lag between validation and commercial rollout, DDR6 modules and compatible processors aren\u2019t expected to ship until sometime in 2027.<\/p>\n
Doubled clock speeds, but tripled bandwidth<\/h3>\n
DDR6 will launch at speeds ranging from DDR5-8800<\/strong> up to DDR5-17600<\/strong> (these are \u201ceffective clock speeds\u201d of 8.8 to 17.6\u202fGHz, though the real clock rate is much lower). That\u2019s roughly double the speed range of current DDR5 memory. As usual, speeds of the actual shipping modules will start on the lower end initially, with higher speeds introduced gradually over time\u2014and potentially even higher speed grades will be unlocked via overclocking.<\/p>\n But a more notable and fundamental innovation lies beyond just frequency increases. DDR6 will employ the same trick as LPDDR6 by expanding the channel width (or more precisely, what has historically been referred to as a memory controller channel) by 50%. Whereas today a standard DDR5 module features a 64-bit width composed of two 32-bit (sub)channels, DDR6 will use 24-bit (sub)channels, but four of them per module.<\/p>\n This expands each module\u2019s total bus width to 96 bits, meaning desktop and notebook platforms\u2014traditionally running on 128-bit (dual-channel) memory\u2014could now operate with 192-bit memory bandwidth. That change alone boosts throughput by 50%, and when paired with the higher effective clocks, overall bandwidth could triple compared to DDR5.<\/p>\n Because this kind of data bus width is unusual for PCs, it will likely adopt the same mechanism as LPDDR6, where each 24-bit subchannel is accessed in bursts whose length has also been increased by 50%\u2014from 8 to 12 cycles. This means the granularity of read or write operations will now be 288 bits. Out of that, 256 bits are reserved for actual data, which results in a clean, round 32 bytes\u2014a data granularity already standard for PC architecture. The remaining 32 bits could be used for various forms of metadata, including ECC protection. With any luck, this could finally pave the way for memory protection becoming a standard feature in DDR6-equipped systems.<\/p>\n The use of 24-bit sub-channels is a surprise. Previous reports didn\u2019t indicate DDR6 would adopt this radical LPDDR-style structure. But this design choice means DDR6 will actually match LPDDR6 in bandwidth scaling, even if LPDDR6 is expected to continue to lead in the adoption time of particular clock speeds grades. The performance gap between mobile and desktop RAM won\u2019t widen as much as once feared.<\/p>\n Interestingly, TrendForce indicates DDR6 won\u2019t be exclusive to servers. Previous reports hinted that client platforms might drop DDR-type RAM altogether in favor of LPDDR-types. However, it now seems DDR6 will continue in desktops, even as LPDDR6 adoption grows. DDR6 is also expected to appear in high-end laptops, following the same path as DDR5\u2019s current deployment in gaming and workstation notebooks.<\/p>\n One major innovation in DDR6 may be its use of CAMM2 modules\u2014compression-attached memory modules that mount flat to the board. JEDEC is currently working to standardize CAMM2 for DDR6, and it\u2019s possible this will become the primary module format for this memory generation.<\/p>\n While there\u2019s no official confirmation yet that CAMM2 will fully replace traditional DIMMs, that scenario is certainly plausible. CAMM2 offers lower signal impedance and enables higher speeds,\u00a0likely making it\u00a0the preferred choice. Should DIMMs still be supported, they might be limited to lower data rates.<\/p>\n In server hardware, CAMM2 likely won\u2019t be used directly. Instead, an adapted form called SOCAMM (also based on compression mounting) is expected to take over\u2014backed by players like Micron and Nvidia.<\/p>\n DDR6 could represent the biggest leap in system memory since the original DDR debuted\u2014which was almost 25 years ago (and by the launch in 2027, that milestone will have officially passed). The move to 24-bit sub-channels is a defining moment, and if it comes hand-in-hand with CAMM2 adoption and mainstream ECC, the term \u201crevolution\u201d would hardly be an exaggeration.<\/p>\n Sources: TrendForce<\/a>, The Guru<\/a>, Commercial Times<\/a><\/em><\/p>\n English translation and edit by Jozef Dud\u00e1\u0161<\/em><\/p>\n![\"Modul](\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2021\/11\/Modul-DIMM-pameti-DDR5-rozdeleni-na-dva-kanaly.png\")
<\/a>![\"MSI's](\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/05\/GOQ_J1jW4AA4AT6.jpg\")
<\/a>DDR6 will be in PCs\u2014LPDDR6 won\u2019t replace it<\/h3>\n
\u2026but with CAMM2 modules?<\/h3>\n
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