{"id":279666,"date":"2026-07-31T12:00:14","date_gmt":"2026-07-31T10:00:14","guid":{"rendered":"https:\/\/www.hwcooling.net\/?p=279666\/"},"modified":"2026-08-20T20:49:15","modified_gmt":"2026-08-20T18:49:15","slug":"how-does-a-processor-work-intended-for-secondary-schools","status":"publish","type":"post","link":"https:\/\/www.hwcooling.net\/en\/how-does-a-processor-work-intended-for-secondary-schools\/","title":{"rendered":"How Does a Processor Work? Intended for Secondary Schools"},"content":{"rendered":"<p><!--nextpage-->The processor, also referred to as the central processing unit (CPU), is the most fundamental and the most important part of a computer. It is the part that executes all tasks (instructions) that are fed to the computer through program code. At the same time, peripheral devices, RAM and storage (hard drives, SSDs, oreven tape in the past) are connected to it in various ways. It is therefore truly the central element of a computer.<!--more--><\/p>\n<div style=\"margin: 5px 5px 15px 5px; padding: 5px; border: 1px dashed #549AFF; background: #f4f8fe;\"><strong>Introductory note:<\/strong> The following content was created as supplementary material for the HWCooling Techtour &#8217;26 educational displays. We produced and supplied schools with display boards (or posters, if you prefer&#8230; these materials are flexible so they are easy to handle) featuring breakdowns of selected hardware components. One of them was the processor, which we will now examine on a general level. The following material is therefore intended to serve educational purposes well. This article can also be accessed quickly via the QR code printed directly on the posters.<\/div>\n<h3 class=\"western\">Role of the CPU<\/h3>\n<p>The processor, referred to as the central processing unit (CPU), is sometimes simplistically compared to the brain of the computer (sometimes the comparison to a heart also appears, but this can be misleading, because one could object that in a computer, the function of blood circulation corresponds more closely to the electrical power supply, while the core function of a computer is more akin to thinking). The comparison to a brain isn&#8217;t perfect either, because the brain also handles long-term and short-term memory\u2014whereas in a computer, these functions are handled not by the central processing unit, but by storage and RAM.<\/p>\n<p>In computer science, the processor (CPU) is the component of the computer that executes the program\u2014that is, the individual machine instructions that make up the program. At the same time, it must handle the inputs and outputs of data that control the program or with which the program works or which it produces. The CPU is therefore the most important element forming any computer and the most important part of its functionality (though not the entirety; the storage and operating memory functions, as well as the physical devices that facilitate various inputs into the computer and outputs out of it, are still needed).<\/p>\n<h3 class=\"western\">First processors built from discrete components and the microprocessor revolution<\/h3>\n<p>Processors or electronic circuits corresponding to their function were initially made up of individual components in historical computers. At the very beginning, they were based on vacuum tubes and relays (computers built from these were very large and less reliable), later on semiconductor transistors. Even a processor composed of separate transistors or later small and medium-scale integrated circuits with multiple transistors in one package (TTL) could take up a considerable size overall and could be composed of several printed circuit boards.<\/p>\n<p>What we imagine a processor to be today appeared under the name <b>microprocessor<\/b> at the beginning of the 1970s. A microprocessor is a processor that is entirely manufactured as an integrated circuit, i.e., a chip. Ideally a single one, but it can also be a few chips (interestingly, in the newest CPUs, the construction from multiple so-called chiplets has started to reappear). The first microprocessor is usually considered to be the rather limited 4-bit Intel 4004 for calculators from 1971. However, at the same time, several candidates from various companies were under development, and Intel 4004 was simply the first to market.<\/p>\n<p>Microprocessors were revolutionary for the development of computers and all advanced electronics and technology derived from them. For some time in the 1970s and early 1980s, the use of processors built from discrete components persisted in more powerful, so-called mainframe computers and minicomputers, until the capabilities and performance of microprocessors (which was initially inferior) surpassed the possibilities of TTL-based processors after this transitional period.<\/p>\n<figure id=\"attachment_215339\" aria-describedby=\"caption-attachment-215339\" style=\"width: 795px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Procesory-Intel-286-1.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-215339 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Procesory-Intel-286-1.jpg\" alt=\"Historical Intel 286 processors from 1982 (Source: Intel)\" width=\"795\" height=\"526\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Procesory-Intel-286-1.jpg 795w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Procesory-Intel-286-1-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Procesory-Intel-286-1-300x198.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Procesory-Intel-286-1-768x508.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Procesory-Intel-286-1-600x398.jpg 600w\" sizes=\"auto, (max-width: 795px) 100vw, 795px\" \/><\/a><figcaption id=\"caption-attachment-215339\" class=\"wp-caption-text\">Historical Intel 286 processors from 1982 (Source: Intel)<\/figcaption><\/figure>\n<p>Over time, however, continuous improvements and progress in microprocessors, driven by advancements in manufacturing technologies, enabled the rapid development of sophisticated architectures, opened up the possibility of using an ever-increasing number of transistors, and generally achieving better and better performance. All this while simultaneously reducing cost and simplifying the manufacturing of the entire computer. Microprocessors therefore gradually became the only form of processors used during the 1980s. All today&#8217;s processors (CPUs) are microprocessors, but we usually no longer use this longer term.<\/p>\n<h3 class=\"western\">Processor and cores<\/h3>\n<p>The historically developed concept of a computer worked with a processor that processed one program (process), i.e., in a single thread\u2014so-called serially. However, computers with multiple processors (each in its own socket on the motherboard) running simultaneously were gradually developed, allowing multiple threads (processes) to run simultaneously, i.e., in parallel. Multi-processor systems are still encountered in servers, designated for example &#8220;2S&#8221;, &#8220;4S&#8221;, &#8220;8S&#8221; according to the number of processors (the letter S stands for socket\u2014these designations literally state the number of processor sockets on the computer&#8217;s motherboard).<\/p>\n<p>In the early years of the 21st century, dual- and multi-core processors appeared. In personal computers, this was in 2005 with AMD Athlon 64 and Intel Pentium D processors. A processor with multiple cores means that within a single unit designated as a processor, several CPUs\/processors are actually integrated in parallel, which can simultaneously process their own processes\/threads. This is essentially a merger of the earlier multi-processor system into a single processor that occupies just one socket on the motherboard.<\/p>\n<figure id=\"attachment_202583\" aria-describedby=\"caption-attachment-202583\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/08\/amd-ryzen-9-9950x_04.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-202583 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/08\/amd-ryzen-9-9950x_04-1024x683.jpg\" alt=\"The Ryzen 9 9950X processor integrates 16 cores into a single package\" width=\"640\" height=\"427\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/08\/amd-ryzen-9-9950x_04-1024x683.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/08\/amd-ryzen-9-9950x_04-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/08\/amd-ryzen-9-9950x_04-300x200.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/08\/amd-ryzen-9-9950x_04-768x512.jpg 768w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-202583\" class=\"wp-caption-text\">The Ryzen 9 9950X processor integrates 16 cores into a single package<\/figcaption><\/figure>\n<p>These individual processors have since been called cores, and the term &#8220;processor&#8221; today refers to the whole unit that aggregates all the cores. Again, it can be said that today almost all standard processors are multi-core; exceptions would only be found in more specialized deployments (embedded devices and processor cores in microcontrollers).<\/p>\n<h3 class=\"western\">From microprocessor to &#8220;SoC&#8221;<\/h3>\n<p>In addition to the transition from earlier purely single-core processors to today&#8217;s multi-core ones, processors have undergone another transformation starting roughly at the beginning of the 21st century, evolving from a component that implemented only the functionality traditionally associated with the concept of a processor (in the sense of the CPU, that central processing unit) into a chip that integrates many other functions that were gradually added to it.<\/p>\n<p>Controllers for various interfaces and connectivity which used to be provided by an external chipset began to be moved onto the CPU chip (starting with the memory controller), as did entire peripherals, such as a graphics adapter and accelerator (i.e., a GPU), or network adapters.<\/p>\n<figure id=\"attachment_116818\" aria-describedby=\"caption-attachment-116818\" style=\"width: 892px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/\u010cip-AMD-mendocino-1600-e1663876403310.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-116818 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/\u010cip-AMD-mendocino-1600-e1663876403310.jpg\" alt=\"The Mendocino SoC used in Ryzen 7020U processors. A single chip includes CPU, GPU, and all chipset components and connectivity controllers (Source: AMD)\" width=\"892\" height=\"888\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/\u010cip-AMD-mendocino-1600-e1663876403310.jpg 892w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/\u010cip-AMD-mendocino-1600-e1663876403310-300x300.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/\u010cip-AMD-mendocino-1600-e1663876403310-768x765.jpg 768w\" sizes=\"auto, (max-width: 892px) 100vw, 892px\" \/><\/a><figcaption id=\"caption-attachment-116818\" class=\"wp-caption-text\">The Mendocino SoC used in Ryzen 7020U processors. A single chip includes CPU, GPU, and all chipset components and connectivity controllers (Source: AMD)<\/figcaption><\/figure>\n<p>This creates a type of processor called an <b>SoC<\/b> (<i>system on a chip<\/i>). This abbreviation means that a single processor (chip) integrates all or almost all of the functionality that a computer requires. This definition usually does not include storage and RAM in SoCs; the processor typically does not contain these components, so in practice, to build a computer you need not only the SoC, but also RAM and an SSD, as well as some motherboard or another way to connect them.<\/p>\n<p>The SoC designation is most commonly used today for mobile processors with ARM architecture in phones and mobile devices, but current x86 processors in personal computers commonly cover practically the same complete computer functionality these days and can also be considered full-fledged SoCs, although the term is used less frequently for them.<\/p>\n<p><em><strong>The article continues on the next page&#8230;<\/strong><\/em><\/p>\n<p><script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script>\n<!-- responsive -->\n<ins class=\"adsbygoogle\"\n     style=\"display:block;background-color:transparent\"\n     data-ad-client=\"ca-pub-8150419924824893\"\n     data-ad-slot=\"6522017574\"\n     data-ad-format=\"auto\"><\/ins>\n<script>\n(adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n&#10240;<\/p>\n<p><!--nextpage-->The processor, also referred to as the central processing unit (CPU), is the most fundamental and the most important part of a computer. It is the part that executes all tasks (instructions) that are fed to the computer through program code. At the same time, peripheral devices, RAM and storage (hard drives, SSDs, oreven tape in the past) are connected to it in various ways. It is therefore truly the central element of a computer.<!--more--><\/p>\n<p>Now we will look at the various components that are integrated into a processor (or a SoC) today. A typical modern processor consists of a single chip in the case of a traditional &#8220;monolithic&#8221; microprocessor, but recently also of multiple chips again\u2014these are then called <b>chiplets<\/b>, with the chiplets being parts that together form the complete functionality that would otherwise be implemented by a single chip. Intel uses the term tile for its products instead of chiplet, but the meaning is the same.<\/p>\n<figure id=\"attachment_2853\" aria-describedby=\"caption-attachment-2853\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2017\/09\/operation-kaby-lake-cooling-the-chip-in-24-ways-01.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"noborder wp-image-2853 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2017\/09\/operation-kaby-lake-cooling-the-chip-in-24-ways-01-1024x479.jpg\" alt=\"Processor with the integrated heat spreader (IHS) removed. The adhesive holding the IHS is visible on the green substrate. A single monolithic silicon chip is in the center. Note the remains of thermal paste. Material ensuring heat transfer must be applied between the IHS and the chip\" width=\"640\" height=\"299\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2017\/09\/operation-kaby-lake-cooling-the-chip-in-24-ways-01-1024x479.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2017\/09\/operation-kaby-lake-cooling-the-chip-in-24-ways-01-300x140.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2017\/09\/operation-kaby-lake-cooling-the-chip-in-24-ways-01-768x359.jpg 768w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-2853\" class=\"wp-caption-text\">Processor with the integrated heat spreader (IHS) removed. The adhesive holding the IHS is visible on the green substrate. A single monolithic silicon chip is in the center. Note the remains of thermal paste. Material ensuring heat transfer must be applied between the IHS and the chip<\/figcaption><\/figure>\n<p>Dividing a chip into chiplets is not an outdated relic of the past, but a consequence of the fact that the increasing complexity of microprocessors is bumping against the limits of the newest manufacturing processes for chip production. This addresses such issues as the newest chip technologies being very expensive, or less suitable for implementing certain types of circuits (analog circuits and physical layers of interfaces, for example). Dividing the processor into two chiplets then allows, for example, placing the CPU cores, which benefit from the newest technology, into one chiplet manufactured by the newest\u00a0 leading-edge process, while placing analog functionality or functionality where performance is not critical into the second chiplet manufactured by an older mature process. Manufacturing part of the resulting area with an older chip manufacturing technology can save production costs today, because newer silicon processes may have a higher price per transistor compared to older ones (Moore&#8217;s Law postulating that prices per transistor keeps falling with new technologies, no longer applies to advanced process nodes).<\/p>\n<figure id=\"attachment_17688\" aria-describedby=\"caption-attachment-17688\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-17688 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka-1024x680.jpg\" alt=\"An AMD Ryzen 3000 generation processor with the IHS removed shows two CPU chiplets. The third larger silicon die is the I\/O chiplet, containing, for example, memory and PCI Express controllers (Source: AMD)\" width=\"640\" height=\"425\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka-1024x680.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka-300x199.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka-768x510.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka-600x398.jpg 600w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka-872x579.jpg 872w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2019\/06\/AMD-Ryzen-3000-Matisse-Am4-procesor-bez-IHS-opoutavka.jpg 1920w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-17688\" class=\"wp-caption-text\">An AMD Ryzen 3000 generation processor with the IHS removed shows two CPU chiplets. The third larger silicon die is the I\/O chiplet, containing, for example, memory and PCI Express controllers (Source: AMD)<\/figcaption><\/figure>\n<p>Last but not least, dividing the processor into multiple chiplets can allow for increased performance\u2014the entire composite CPU can then have a larger silicon area than can be manufactured as a single monolithic chip (the maximum area that fabs are capable of producing chips with is given by the reticle limit, which is around 800 mm\u00b2).<\/p>\n<h3 class=\"western\">Physical package<\/h3>\n<p>The chip or chiplets must be housed in a so-called package for use. This consists of a substrate, which is an organic printed circuit board, onto which the chip is soldered using pads on the underside of its metal layers (using the modern &#8220;flip-chip&#8221; method; before that, thin wires were instead led from the pads on the chip&#8217;s metal layers). The substrate routes electrical conductors from the chip&#8217;s metal layers themselves to the external contacts of the entire processor, which then connect to the motherboard.<\/p>\n<figure id=\"attachment_88602\" aria-describedby=\"caption-attachment-88602\" style=\"width: 754px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/02\/Intel-Celeron-N5105-10nm-generace-Jasper-Lake-na-desce-firmy-GigaIPC.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-88602 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/02\/Intel-Celeron-N5105-10nm-generace-Jasper-Lake-na-desce-firmy-GigaIPC.jpg\" alt=\"An SoC in a BGA package soldered to the motherboard: Intel Celeron N5105 on a GigaIPC iTXL-5105A board (Source: GigaIPC)\" width=\"754\" height=\"507\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/02\/Intel-Celeron-N5105-10nm-generace-Jasper-Lake-na-desce-firmy-GigaIPC.jpg 754w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/02\/Intel-Celeron-N5105-10nm-generace-Jasper-Lake-na-desce-firmy-GigaIPC-300x202.jpg 300w\" sizes=\"auto, (max-width: 754px) 100vw, 754px\" \/><\/a><figcaption id=\"caption-attachment-88602\" class=\"wp-caption-text\">An SoC in a BGA package soldered to the motherboard: Intel Celeron N5105 on a GigaIPC iTXL-5105A board (Source: GigaIPC)<\/figcaption><\/figure>\n<p>The package can be soldered directly to the motherboard\u2014this is called a <b>BGA<\/b> type package (ball grid array, named for the solder balls applied to the contacts on the underside). In processors for desktop computers, a package intended for socket installation is often used instead, with pins on the underside of the substrate\u2014this is a <strong>PGA<\/strong> package (pin grid array).<\/p>\n<p>Newer processors tend to use an <strong>LGA<\/strong> package (land grid array), which means that there are only contact pads on the underside of the substrate and the pins that will contact them are in the motherboard socket. PGA and LGA packages allow for easy processor replacement even by the end users themselves.<\/p>\n<figure id=\"attachment_31004\" aria-describedby=\"caption-attachment-31004\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-9.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-31004 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-9-1024x576.jpg\" alt=\"Left: processor with LGA package, right: PGA\" width=\"640\" height=\"360\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-9-1024x576.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-9-300x169.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-9-768x432.jpg 768w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-31004\" class=\"wp-caption-text\">Left: processor with LGA package, right: PGA<\/figcaption><\/figure>\n<figure id=\"attachment_239080\" aria-describedby=\"caption-attachment-239080\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-13.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-239080 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-13-1024x576.jpg\" alt=\"Left: processor with LGA package, right: PGA\" width=\"640\" height=\"360\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-13-1024x576.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-13-300x169.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-13-768x432.jpg 768w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-239080\" class=\"wp-caption-text\">Left: processor with LGA package, right: PGA<\/figcaption><\/figure>\n<p>Historical microprocessors could also have simpler packages, for example DIP (dual inline package), which is a package with two rows of pins on the sides, from which the colloquial designation of chips as &#8220;bugs&#8221; is derived. Some historical processors came in a slot form factor similar to an expansion card (Slot 1 for Intel Pentium II and III processors, Slot A for AMD Athlon processors). In this case, it was essentially a processor in a BGA package, soldered onto another printed circuit board, on which there could be additional chips\u2014particularly external cache (L2 cache) chips.<\/p>\n<figure id=\"attachment_116312\" aria-describedby=\"caption-attachment-116312\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/Intel-Celeron.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-116312 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/Intel-Celeron-1024x459.jpg\" alt=\"Intel Celeron also codenamed &quot;Mendocino&quot; (no relation to the newer AMD SoC) in Slot 1 form factor, which was introduced in card form factor due to the external second-level cache required by Pentium II processors. Celerons were also manufactured in this form factor despite not using the external cache (photo: ExtraHardware, Marek Havelka)\" width=\"640\" height=\"287\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/Intel-Celeron-1024x459.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/Intel-Celeron-300x135.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/Intel-Celeron-768x345.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2022\/09\/Intel-Celeron.jpg 2042w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-116312\" class=\"wp-caption-text\">Intel Celeron also codenamed &#8220;Mendocino&#8221; (no relation to the newer AMD SoC) in Slot 1 form factor, which was introduced in card form factor due to the external second-level cache required by Pentium II processors. Celerons were also manufactured in this form factor despite not using the external cache (photo: ExtraHardware, Marek Havelka)<\/figcaption><\/figure>\n<h3 class=\"western\">Heat spreaders and protective features<\/h3>\n<p>Desktop processors usually have the chip on the substrate covered by a metal lid called an integrated heat spreader (IHS). This name comes from the fact that the top surface of the IHS is significantly larger than the surface of the chip itself, so it transfers heat to the heatsink base mounted on the processor through a larger contact area. However, this IHS also provides the fragile chip with protection against mechanical damage, for example from uneven heatsink pressure. The disadvantage is that the IHS layer hampers (slows down) heat dissipation from the chip to the heatsink somewhat. Laptop processors often lack an IHS and instead use a metal frame around the processor to ensure uniform and safe heatsink mounting on the silicon.<\/p>\n<figure id=\"attachment_239075\" aria-describedby=\"caption-attachment-239075\" style=\"width: 3840px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-8.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-239075 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-8.jpg\" alt=\"Metal heat spreaders covering the chip of the processors from the previous example\" width=\"3840\" height=\"2160\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-8.jpg 3840w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-8-300x169.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-8-768x432.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2020\/06\/intel-10th-gen-8-1024x576.jpg 1024w\" sizes=\"auto, (max-width: 3840px) 100vw, 3840px\" \/><\/a><figcaption id=\"caption-attachment-239075\" class=\"wp-caption-text\">Metal heat spreaders covering the chip of the processors from the previous example<\/figcaption><\/figure>\n<p>Practically all processors for personal computers necessarily require a heatsink for their operation, because their work converts electricity into heat and the thermal output (in watts) is typically much higher than what could be safely dissipated into the surrounding environment. The processor must therefore be cooled to prevent overheating and destruction. The value of thermal output (power consumption) that the processor requires to be cooled is given as <b>TDP<\/b> (Thermal Design Power). The cooling used must be capable of dissipating at least the specified TDP of the processor, or ideally a higher value.<\/p>\n<p>Thermal interface material (thermal grease, or liquid metal solution) or a special thermal pad must be applied between the IHS and the heatsink base to improve heat dissipation. The processor itself already has thermal grease or a soldered joint between its silicon chip and the IHS added during manufacturing.<\/p>\n<p><em><strong>The article continues on the next page&#8230;<\/strong><\/em><\/p>\n<p><script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script>\n<!-- responsive -->\n<ins class=\"adsbygoogle\"\n     style=\"display:block;background-color:transparent\"\n     data-ad-client=\"ca-pub-8150419924824893\"\n     data-ad-slot=\"6522017574\"\n     data-ad-format=\"auto\"><\/ins>\n<script>\n(adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n&#10240;\u2800<\/p>\n<p><!--nextpage-->The processor, also referred to as the central processing unit (CPU), is the most fundamental and the most important part of a computer. It is the part that executes all tasks (instructions) that are fed to the computer through program code. At the same time, peripheral devices, RAM and storage (hard drives, SSDs, oreven tape in the past) are connected to it in various ways. It is therefore truly the central element of a computer.<!--more--><\/p>\n<h3 class=\"western\">Cores<\/h3>\n<p>Within the processor chip itself, we can distinguish blocks providing various functionalities. The most essential component is the so-called cores, which perform the processing of program instructions, i.e., the core functionality of the CPU. From a functional standpoint, each core is essentially one processor\u2014today&#8217;s processor practically always includes multiple CPUs (cores). We will discuss the functioning of the core itself in the last chapter.<\/p>\n<h3 class=\"western\">Caches<\/h3>\n<p>The original concept of a computer assigned working memory to the processor, which evolved into RAM. Quite soon, it was discovered that operating memory usually has lower access speed and data transfer rates than the processor is capable of working at, and the CPU often cannot continue its work because it waits for data to arrive from memory or for sent data to be written to memory.<\/p>\n<p>This problem is solved by caches. Their purpose is that they are smaller but much faster than RAM. The processor can thus keep the most frequently used or currently processed data in them and work with them faster than RAM itself would allow\u2014but changes made to data in the cache must then be written back to the operating memory. Today&#8217;s processors usually have several hierarchies of caches, where the first-level cache has the highest performance (the shortest access time, i.e., latency, and the highest data throughput for reads and writes) because it is closest to the execution and load\/store units in the CPU core, but the lowest capacity, usually single digits to double digits of kilobytes.<\/p>\n<p>The second-level cache has a higher capacity (on the order of hundreds of kilobytes to a few megabytes), but longer latency and lower throughput, and so on. Most commonly, processors have three levels of caches (L1, L2, L3), with the last one being shared by multiple or all cores. Additionally, processors sometimes have a system-level cache (SLC), which is considered distinct from a regular last-level cache because not only CPU cores but also other parts of the processor (SoC), such as NPUs for AI acceleration, can access it. The SLC can sometimes be associated with the memory controller.<\/p>\n<h3 class=\"western\">Interconnection of cores and other blocks<\/h3>\n<p>The cores must be connected to some type of bus or interconnect logic that makes them a single processor. This logic ensures that all cores can access operating memory and synchronize the contents of their caches with it (it is important to ensure that no core works with old contents of RAM after another core has changed it in its cache\u2014this change must first be reflected back to RAM so that other cores do not work with incorrect data values). The interconnect logic in a processor can have various topologies similar to network topologies\u2014it can be fully connected (crossbar switch, where each core has a direct connection to every other), ring (ring bus), or mesh type. Sometimes various combinations are used, for example, pairs of ring interconnections bridged at certain points.<\/p>\n<figure id=\"attachment_279541\" aria-describedby=\"caption-attachment-279541\" style=\"width: 750px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-mesh-propojeni-jader-u-procesoru-Intel-Skylake-X.png\"><img loading=\"lazy\" decoding=\"async\" class=\"noborder wp-image-279541 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-mesh-propojeni-jader-u-procesoru-Intel-Skylake-X.png\" alt=\"Mesh interconnect diagram for the cores and controllers for memory and PCI Express of Intel Skylake-X\/Skylake-SP (1st generation Xeon Scalable) processors (Source: Intel)\" width=\"750\" height=\"560\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-mesh-propojeni-jader-u-procesoru-Intel-Skylake-X.png 750w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-mesh-propojeni-jader-u-procesoru-Intel-Skylake-X-300x224.png 300w\" sizes=\"auto, (max-width: 750px) 100vw, 750px\" \/><\/a><figcaption id=\"caption-attachment-279541\" class=\"wp-caption-text\">Mesh interconnect diagram for the cores and controllers for memory and PCI Express of Intel Skylake-X\/Skylake-SP (1st generation Xeon Scalable) processors (Source: Intel)<\/figcaption><\/figure>\n<p>Similarly to how the processor contains interconnect logic for transferring data, it must also contain other systems: for example, a system for distributing the clock signal across the chip and a system of conductors that bring electrical current from the motherboard into and distribute it within the chip. Power delivery in modern processors is complex\u2014it requires several different voltage rails and requires very precise voltage regulation (incorrect voltage regulation can easily damage the chip). Large portion of the processor&#8217;s contacts are actually used for delivering voltage and for ground connections today.<\/p>\n<figure id=\"attachment_157785\" aria-describedby=\"caption-attachment-157785\" style=\"width: 1536px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"noborder wp-image-157785 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka.jpg\" alt=\"Chip used in AMD Ryzen 1000 processors. The two identical pink-purple blocks are the blocks with Zen cores (Photo: Fritzchens Fritz)\" width=\"1536\" height=\"1020\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka.jpg 1536w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka-300x199.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka-768x510.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka-1024x680.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka-600x398.jpg 600w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/06\/Amd-Ryzen-cip-Zeppelin-Summit-Ridge-kremik-Fritzchens-Fritz-upoutavka-872x579.jpg 872w\" sizes=\"auto, (max-width: 1536px) 100vw, 1536px\" \/><\/a><figcaption id=\"caption-attachment-157785\" class=\"wp-caption-text\">Chip used in AMD Ryzen 1000 processors. The two identical pink-purple blocks are the blocks with Zen cores (Photo: Fritzchens Fritz)<\/figcaption><\/figure>\n<h3 class=\"western\">Connectivity and memory controllers<\/h3>\n<p>Today&#8217;s processor directly contains blocks providing various connectivity within themselves, which are also connected to the CPU&#8217;s internal interconnect. The most important of these is the memory controller which works with <b>RAM<\/b> on memory modules, driving the memory and performing data accesses. <b>PCI Express<\/b> connectivity controllers provide this standardised hardware interface connectivity, through which peripherals including GPUs, as well as storage in the form of NVMe SSDs, are connected to the processor. An additional chipset (or platform controller hub) is also connected via PCI Express connectivity or its modified derivatives. Processors may also have integrated controllers for USB or other interfaces (I2C, SPI Flash for connecting the firmware chip, and others) and video outputs from their integrated GPU.<\/p>\n<p>Some of this connectivity features are functionality that has moved into the processor from previously separate chipsets. This is why it is sometimes stated that the processor contains an integrated northbridge (by which the integrated PCI Express controller is typically meant) or a southbridge (which refers to USB controllers or SATA interfaces for hard drives, optical drives, and the like). These are historical terms going back to how the individual chips of chipsets in personal computers used to be nicknamed.<\/p>\n<h3 class=\"western\">Integrated peripherals<\/h3>\n<p>Various other functions have been gradually added to processors alongside the CPU cores. Today CPU typically contains an integrated <b>GPU<\/b> providing functions corresponding to a graphics card (using a portion of RAM as graphics memory), although some desktop CPUs and server CPUs do not contain one. More recently, an <b>NPU<\/b>, an accelerator designed for AI workloads, has been added to the processor. Along with the GPU, multimedia blocks (engines) for video compression and decompression may be integrated. In the future, various other components may be added according to the needs of computers\u2014some mobile processors already integrate, for example, a Wi-Fi and Bluetooth wireless connectivity adapter, or a 5G mobile data network modem (these adapters usually require an additional chip for the analog functionality of the radio transmitter and receiver themselves).<\/p>\n<figure id=\"attachment_8633\" aria-describedby=\"caption-attachment-8633\" style=\"width: 3840px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-8633 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz.jpg\" alt=\"14nm Raven Ridge APU chip. The blue block farther from the camera is the block of four Zen cores, while the green-orange blocks closer to the camera belong to the integrated GPU (photo: Fritzchens Fritz)\" width=\"3840\" height=\"2550\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz.jpg 3840w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz-300x199.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz-768x510.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz-1024x680.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz-600x398.jpg 600w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2018\/04\/AMD-Ryzen-APU-Raven-Ridge-AM4-foto-Fritzchens-Fritz-872x579.jpg 872w\" sizes=\"auto, (max-width: 3840px) 100vw, 3840px\" \/><\/a><figcaption id=\"caption-attachment-8633\" class=\"wp-caption-text\">14nm Raven Ridge APU chip. The blue block farther from the camera is the block of four Zen cores, while the green-orange blocks closer to the camera belong to the integrated GPU (photo: Fritzchens Fritz)<\/figcaption><\/figure>\n<h3 class=\"western\">Control units, microcode<\/h3>\n<p>Today&#8217;s SoC is an extremely complex system and usually has some control unit of its own, which contains its own separate embedded core or cores running firmware, or may even have many different firmwares for its various components (referred to as microcode for the CPU cores). These control units and their firmware are not normally visible to the user and their software; they run in the background and ensure the proper initialization and operation of the CPU cores visible to the computer user and various running software. These control units can also implement various security technologies and protections\u2014for example,\u00a0checking authenticity (cryptographic signatures) of firmware and the operating system as they are loaded during computer boot.<\/p>\n<h3 class=\"western\">RAM near the processor<\/h3>\n<p>Main memory (RAM) is a separate component outside the processor, just like permanent storage (SSD, HDD). To save space and for benefits it can bring in reducing power consumption, processors sometimes have RAM chips (usually mobile types like LPDDR, e.g., LPDDR5X) mounted directly on the processor which is referred to as on-package memory. They are not integrated directly into the CPU in the sense of being on the same chip\u2014they are merely soldered onto the same substrate.<\/p>\n<figure id=\"attachment_196558\" aria-describedby=\"caption-attachment-196558\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Intel-Lunar-Lake-upoutavka.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-196558 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Intel-Lunar-Lake-upoutavka-1024x683.jpg\" alt=\"Lunar Lake processor (Intel Core Ultra 200V): An example of a processor with memory mounted in the CPU package. Note the lines on the processor silicon; this is a chiplet SoC\" width=\"640\" height=\"427\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Intel-Lunar-Lake-upoutavka-1024x683.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Intel-Lunar-Lake-upoutavka-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Intel-Lunar-Lake-upoutavka-300x200.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/06\/Intel-Lunar-Lake-upoutavka-768x512.jpg 768w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-196558\" class=\"wp-caption-text\">Lunar Lake processor (Intel Core Ultra 200V): An example of a processor with memory mounted in the CPU package. Note the lines on the processor silicon; this is a chiplet SoC<\/figcaption><\/figure>\n<p>The advantage of this approach is that the conductors are shortened compared to the situation where they first pass through the substrate, then one set of contacts to the printed circuit board forming the motherboard, and only then to the memory chips. From an architectural standpoint, however, this mounting works the same as if the memory were mounted on the motherboard. But it is possible that in the future, integrating memory on the processor package will actually bring faster and more powerful connections between RAM and the CPU than we have today.<\/p>\n<p><em><strong>The article continues on the next page&#8230;<\/strong><\/em><\/p>\n<p><script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script>\n<!-- responsive -->\n<ins class=\"adsbygoogle\"\n     style=\"display:block;background-color:transparent\"\n     data-ad-client=\"ca-pub-8150419924824893\"\n     data-ad-slot=\"6522017574\"\n     data-ad-format=\"auto\"><\/ins>\n<script>\n(adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n&#10240;<\/p>\n<p><!--nextpage-->The processor, also referred to as the central processing unit (CPU), is the most fundamental and the most important part of a computer. It is the part that executes all tasks (instructions) that are fed to the computer through program code. At the same time, peripheral devices, RAM and storage (hard drives, SSDs, oreven tape in the past) are connected to it in various ways. It is therefore truly the central element of a computer.<!--more--><\/p>\n<h3 class=\"western\">Instruction set<\/h3>\n<p>The processor executes machine instructions forming a program, which are not the same as the code written by the programmer\u2014that must first be translated into machine code by a compiler. Machine code corresponds more closely to how the operations are performed by the CPU itself, and its instructions can take many different forms. There are therefore many different so-called instruction sets (also referred to as ISA), which represent a sum of instructions the CPU supports. This set does not have to be static, instead instruction sets usually expand and evolve over time.<\/p>\n<p>Multiple processors typically arise or have arisen based on one particular instruction set, which are then compatible thank to the same instruction set and allow running the same compiled machine code. Such processors then form platforms or families; sometimes we also speak of an &#8220;architecture&#8221; when referring to such families, but this refers to the instruction set&#8217;s architecture, not the architecture of a specific processor core (which is sometimes called a &#8220;microarchitecture&#8221;).<\/p>\n<p>An ecosystem of operating systems and user software that can be run on computers with a processor of a given instruction set therefore forms around CPU instruction sets\u2014for example, the ecosystem of the Windows operating system, Linux, and similar OSes on Intel, AMD, and Zhaoxin processors that use the x86 instruction set (more precisely, its 64-bit version, sometimes referred to as x64). In mobile phones, there is another such an ecosystem around Arm processors.<\/p>\n<h3 class=\"western\">&#8220;Bitness&#8221;<\/h3>\n<p>Older processors are often divided into generations designated as 8-bit, 16-bit, 32-bit, and 64-bit (in the past, however, more exotic &#8220;irregular&#8221; architectures with other &#8220;sizes&#8221; also appeared). This number characterizing the processor can have various meanings. It mainly denoted the size of the operand (the data value being processed, or more precisely the size of the registers into which these values are stored), but also often the ability to address memory (which is the number of bits forming the address that distinguishes the position of data in memory\u2014the number of bits determines how large the maximum memory capacity that can be worked with is). And to make it more complicated, the processor bus used for data input and output also has its own width in bits (often different). For example, the Motorola 68000 was largely a 32-bit processor (having 32-bit registers), but for cost-saving reasons, the first generations had only 24-bit memory addressing and only a 16-bit data bus, so 32-bit values had to be transferred in two cycles.<\/p>\n<p>8-bit microprocessors (which, however, often had 16-bit memory addressing, as 8-bit addresses give an impractically small capacity) powered the first waves of home computers and business computers from the 1970s that were not yet PC-compatible\u2014for example, the Atari 800, Sinclair ZX Spectrum, Commodore C64, and Apple II families. Significant representatives were the Intel 8080, Zilog Z80 (a compatible evolutionary successor), and MOS Technology 6502 microprocesors.<\/p>\n<p>16-bit processors in personal computers emerged around the turn of the 1970s and 1980s and were, for example, the foundation of the first IBM PCs and compatible devices\u00a0(with x86 Intel 8088\/8086\u00a0and Intel 286 processors), from which a large portion of modern computers are derived. Many processors still composed of discrete components were also 16-bit, for example the historically significant DEC PDP-11 computers.<\/p>\n<figure id=\"attachment_154281\" aria-describedby=\"caption-attachment-154281\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/05\/Procesory-AMD-a-Intel-retro-ilustrace-1600.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-154281 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/05\/Procesory-AMD-a-Intel-retro-ilustrace-1600-1024x576.jpg\" alt=\"Historical 32-bit x86 processors from AMD and Intel and a 64-bit Athlon 64 (photo: Jan Ol\u0161an)\" width=\"640\" height=\"360\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/05\/Procesory-AMD-a-Intel-retro-ilustrace-1600-1024x576.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/05\/Procesory-AMD-a-Intel-retro-ilustrace-1600-300x169.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/05\/Procesory-AMD-a-Intel-retro-ilustrace-1600-768x432.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/05\/Procesory-AMD-a-Intel-retro-ilustrace-1600.jpg 1920w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-154281\" class=\"wp-caption-text\">Historical 32-bit x86 processors from AMD and Intel and a 64-bit Athlon 64 (photo: Jan Ol\u0161an)<\/figcaption><\/figure>\n<p>Relatively quickly, in the 1980s, computers transitioned to 32-bit processors (for which 32-bit addresses allow up to 4 GB of RAM), which lasted for a longer period. Examples: Intel 386, 486, Pentium and later, AMD K5, K6, Athlon, the Motorola 68000 family, older generations of MIPS, IBM POWER\/PowerPC, Sun SPARC processors.<\/p>\n<p>Around the turn of the century, there was a transition to 64-bit processors, which theoretically allow up to 16 EB (exabytes, i.e., 16,777,216 TB) of memory, which will likely be sufficient for quite a long time. RISC processors were the first to transition to 64-bit architectures; the Athlon 64 and Opteron from AMD were the \u00a0first 64-bit x86 processors for personal computers. Practically all subsequent AMD and Intel models (from late Pentium 4 and Core 2 models onward) are also 64-bit. Arm processors in mobile phones were the last to transition to a 64-bit instruction set, starting around 2013\u20132014; since then, this distinction has only been applicable in microcontrollers and embedded cores and chips, where 32bit or even 8-bit architectures still have their use.<\/p>\n<figure id=\"attachment_185504\" aria-describedby=\"caption-attachment-185504\" style=\"width: 400px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/02\/AMD-Athlon-64.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"noborder wp-image-185504 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/02\/AMD-Athlon-64.jpg\" alt=\"AMD Athlon 64, the first x86 processor with a 64-bit architecture\" width=\"400\" height=\"292\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/02\/AMD-Athlon-64.jpg 400w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/02\/AMD-Athlon-64-300x219.jpg 300w\" sizes=\"auto, (max-width: 400px) 100vw, 400px\" \/><\/a><figcaption id=\"caption-attachment-185504\" class=\"wp-caption-text\">AMD Athlon 64, the first x86 processor with a 64-bit architecture<\/figcaption><\/figure>\n<h3 class=\"western\">Prominent instruction sets<\/h3>\n<p>The most important instruction sets used today are the aforementioned x86 and Arm. <b>x86<\/b> (x64) derives from the Intel 8086 processor (from 1976) and through gradual evolution gained new instructions and more powerful implementations up to the present day. Alongside Intel, other companies began manufacturing CPUs with this architecture at the time when the 8088 processor (a cheaper version of the 8086) was chosen for the IBM PC, which established the personal computer platform used to this day. The most significant of these other manufacturers is AMD, which has stayed in this market since the 1980s and has become the second, fully-fledged supplier of processors of this instruction set for PCs, also co-steering its future direction (AMD, not Intel, for example, developed the 64-bit evolution of the architecture). The companies recently formed a consortium to harmonize x86 development.<\/p>\n<p>The <b>Arm<\/b> instruction set appeared slightly later, in 1985, but it only established its current stronghold in the mobile phone market later. The currently used Armv8 and Armv9 versions, however, date only from this century and are a newly designed instruction set, rather than deriving from the line of previous generations of the Arm set\u2014they are not compatible with them). While x86 is historically a CISC-type set, Arm has some RISC features (constant instruction length), but today it already has a large number of often complex instructions, so it no longer corresponds to RISC principles.<\/p>\n<figure id=\"attachment_248644\" aria-describedby=\"caption-attachment-248644\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/06\/ARM-procesor-Nvidia-GB10-1600.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-248644 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/06\/ARM-procesor-Nvidia-GB10-1600-1024x576.jpg\" alt=\"Nvidia RTX Spark Arm processor, also known as Nvidia GB10 (Author: Gigabyte)\" width=\"640\" height=\"360\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/06\/ARM-procesor-Nvidia-GB10-1600-1024x576.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/06\/ARM-procesor-Nvidia-GB10-1600-300x169.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/06\/ARM-procesor-Nvidia-GB10-1600-768x432.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/06\/ARM-procesor-Nvidia-GB10-1600.jpg 1200w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-248644\" class=\"wp-caption-text\">Nvidia RTX Spark Arm processor, also known as Nvidia GB10 (Author: Gigabyte)<\/figcaption><\/figure>\n<p>Currently, the <b>RISC-V<\/b> instruction set is gaining significance, having originated in an academic environment and being more in line with the original RISC concept than today&#8217;s Arm versions, and has been gradually moved to being implemented in real manufactured processors over the last 10 years. Its advantage is that processors based on it can be manufactured by anyone (unlike x86) and it is not subject to any licensing fees (unlike Arm). Currently, there are no high-performance RISC-V processors for personal computers and servers on the market yet, and the software ecosystem for these areas is also lacking, so the use of processors based on the RISC-V instruction set is currently essentially limited to the embedded device market, embedded cores integrated into chips with other functions (for example, in SSD controllers), and microcontrollers.<\/p>\n<figure id=\"attachment_272067\" aria-describedby=\"caption-attachment-272067\" style=\"width: 554px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/02\/Milk-V-Titan.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-272067 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/02\/Milk-V-Titan.jpg\" alt=\"Milk-V Titan board with a RISC-V architecture processor. Such hardware currently serves mainly for development; this instruction set has not yet found application in client devices (Author: Milk-V)\" width=\"554\" height=\"509\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/02\/Milk-V-Titan.jpg 554w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/02\/Milk-V-Titan-300x276.jpg 300w\" sizes=\"auto, (max-width: 554px) 100vw, 554px\" \/><\/a><figcaption id=\"caption-attachment-272067\" class=\"wp-caption-text\">Milk-V Titan board with a RISC-V architecture processor. Such hardware currently serves mainly for development; this instruction set has not yet found application in client devices (Author: Milk-V)<\/figcaption><\/figure>\n<h3 class=\"western\">Prominent instruction sets of the past<\/h3>\n<p>Some prominent instruction sets no longer active today include, for example, the Motorola 68000 (CISC) instruction set; these processors were used by many discontinued computers competing with the PC (Apple, Atari ST, Amiga) as well as game consoles. For a time, several RISC instruction sets were successful in the market: MIPS, SPARC from Sun, and PowerPC or POWER from IBM (alongside which it was manufactured by Motorola and later Freescale); however, they eventually largely lost their markets and significance and were replaced by processors with x86 and Arm instruction sets. A partial exception is Power processors, which survive in proprietary IBM servers and keep their own low-volume market (for now, at least).<\/p>\n<figure id=\"attachment_171508\" aria-describedby=\"caption-attachment-171508\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Kremik-procesoru-IBM-Power10.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"size-large wp-image-171508\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Kremik-procesoru-IBM-Power10-1024x683.jpg\" alt=\"\" width=\"640\" height=\"427\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Kremik-procesoru-IBM-Power10-1024x683.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Kremik-procesoru-IBM-Power10-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Kremik-procesoru-IBM-Power10-300x200.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Kremik-procesoru-IBM-Power10-768x512.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Kremik-procesoru-IBM-Power10.jpg 1360w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-171508\" class=\"wp-caption-text\">Silicon of the IBM Power10 processor (Author: IBM, via HardwareLuxx)<\/figcaption><\/figure>\n<p>A different instruction set is a barrier to software compatibility, and less widespread instruction sets have smaller software ecosystems, which leads to such platforms less competitive with the large and widely established ecosystems of major instruction sets. This is the main reason why these other instruction sets did not survive in the market.<\/p>\n<h3 class=\"western\"><i>History: What was the CISC versus RISC rivalry about?<\/i><\/h3>\n<p>Processors and microprocessors initially developed into a form where they had relatively large numbers of instructions, some of which performed quite complex operations like square root or division that took many cycles. Instructions also had varying lengths (different numbers of bytes). This concept, or rather the processors that has gradually evolved into this form mostly spontaneously, was later retrospectively labeled CISC (complex instruction set computer).<\/p>\n<p>Around the turn of the 1970s and 1980s, the concept of RISC processors began to be promoted in contrast to what was retrospectively labeled CISC. RISC processors, on the other hand, have a reduced instruction set (RISC = reduced instruction set computer). This meant that the number of instructions was limited; for example, instructions performing operations with values in memory were removed (instead, the compiler used separate instructions to load data from memory into registers and then an instruction working with the register). Processors did not have complex instructions like division and sometimes not even multiplication, which the software compiler had to replace with a sequence of basic operations at the software level. An important feature was that instructions had a constant length.<\/p>\n<p>The benefit of these simplifications was supposed to be that processors would be easier to design and require fewer transistors, and moreover, advanced techniques like pipelining and out-of-order execution could be used with them. And thus stripping down the processor&#8217;s capabilities was ultimately supposed to lead to higher practical performance.<\/p>\n<p>In the 1980s and 1990s, it was assumed that RISC processors would displace older CISC instruction sets including x86. However, it turned out that thanks to the broad market for x86 processors, these processor manufacturers had sufficient resources and motivation to improve their architecture so as to overcome the disadvantages of CISC. Part of this was that processors began internally decomposing many complex operations into simple operations similarly to RISC processors. At the same time, RISC instruction sets tended to gradually increase the number of instructions, and some complex instructions were added back for performance reasons, so the differences gradually blurred. Intel and AMD processors ultimately won the competitive battle against various RISC processors also because they had a larger market behind them.<\/p>\n<figure id=\"attachment_171509\" aria-describedby=\"caption-attachment-171509\" style=\"width: 1600px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Deska-Raptor-Computing-Systems-Talos-II-pro-procesory-IBM-Power9.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"noborder wp-image-171509 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Deska-Raptor-Computing-Systems-Talos-II-pro-procesory-IBM-Power9.jpg\" alt=\"Raptor Computing Systems Talos II board for IBM Power9 processors (Author: Raptor Computing Systems)\" width=\"1600\" height=\"900\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Deska-Raptor-Computing-Systems-Talos-II-pro-procesory-IBM-Power9.jpg 1600w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Deska-Raptor-Computing-Systems-Talos-II-pro-procesory-IBM-Power9-300x169.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Deska-Raptor-Computing-Systems-Talos-II-pro-procesory-IBM-Power9-768x432.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2023\/10\/Deska-Raptor-Computing-Systems-Talos-II-pro-procesory-IBM-Power9-1024x576.jpg 1024w\" sizes=\"auto, (max-width: 1600px) 100vw, 1600px\" \/><\/a><figcaption id=\"caption-attachment-171509\" class=\"wp-caption-text\">Raptor Computing Systems Talos II board for IBM Power9 processors (Author: Raptor Computing Systems)<\/figcaption><\/figure>\n<p>Today, it can be said that the distinction between RISC and CISC architectures has practically lost its meaning, because virtually all processors on the market today are &#8220;something in between&#8221; these concepts. Microarchitectures implementing today&#8217;s Arm and Power instruction sets will be similarly complex as x86 if they are to have the same performance. Of the original RISC design features, the main trait that has persistent significance is the use of instructions with a constant width, which simplifies the design of instruction decoders and helps achieving high performance\u00a0more easily (as opposed to x86 processors with their variable instruction length).<\/p>\n<h3 class=\"western\">FPU, SIMD, and matrix extensions<\/h3>\n<p>Expanding the capabilities of processors is something that has happened and continues to happen with practically all instruction sets. In addition to the original integer and arithmetic-logic operations performed by ALUs, instructions working with floating-point data were later added. Support for these operations, however, was not always part of the processor. For a time, it was provided by separate FPU (floating point unit) chips implementing these instructions (x86 platform FPUs were designated 287, 387, or 487 by Intel, hence these instructions are referred to as x87).<\/p>\n<p>Such chips were called coprocessors in contrast to the processor itself. Initially, they were not at all mandatory; personal computers did not have to include them, but in the 486 and Pentium generations, they became a fixed part of the core and x87 instructions part of the x86 instruction set. However, the coprocessor-original character is still visible, for example, in that they use different registers.<\/p>\n<p>SIMD units added laterdirectly \u00a0can also be classified as coprocessors, although they are practically always integrated into the CPU core. They began to appear widely in CPUs in the second half of the 1990s. SIMD stands for &#8220;single instruction, multiple data,&#8221; and the purpose of these instructions is to always perform given operations on multiple data at once, for which they have a wider register\u2014for example, a 128-bit register can hold four 32-bit or up to sixteen 8-bit values (which can be thought of as a vector), and one instruction can then perform, for example, addition with all values in such registers at once. SIMD instructions can therefore significantly improve performance in working with multimedia, graphics, or large amounts of numerical computations, especially when code is manually optimized to use them (vectorization; automatic use of SIMD instructions by the software compiler is called autovectorization).<\/p>\n<p>In x86 processors for PCs, the first SIMD capability to appear was the MMX extension in Pentium MMX processors in 1995, which had a register width of 64 bits and used the same registers used for x87 operations in the FPU. Later, more advanced SIMD extension were gradually added: SSE through SSE4s with a register width of 128 bits (first in 1999), AVX through AVX2 with a width of 256 bits (2011), and finally the AVX-512 family of extensions with a width of 512 bits (first in 2017; in the future, the designation will transition to AVX10). Comprehensive and broad support for SIMD operations and their high performance due to the large register width (especially with AVX-512) is one of the advantages of x86 processors.<\/p>\n<figure id=\"attachment_227726\" aria-describedby=\"caption-attachment-227726\" style=\"width: 1213px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/03\/Nov\u011b-definovan\u00e9-instrukce-AVX10.png\"><img loading=\"lazy\" decoding=\"async\" class=\"noborder wp-image-227726 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/03\/Nov\u011b-definovan\u00e9-instrukce-AVX10.png\" alt=\"AVX, AVX2, AVX-512, and AVX10 SIMD instructions (Source: Intel)\" width=\"1213\" height=\"469\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/03\/Nov\u011b-definovan\u00e9-instrukce-AVX10.png 1213w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/03\/Nov\u011b-definovan\u00e9-instrukce-AVX10-300x116.png 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/03\/Nov\u011b-definovan\u00e9-instrukce-AVX10-768x297.png 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2025\/03\/Nov\u011b-definovan\u00e9-instrukce-AVX10-1024x396.png 1024w\" sizes=\"auto, (max-width: 1213px) 100vw, 1213px\" \/><\/a><figcaption id=\"caption-attachment-227726\" class=\"wp-caption-text\">AVX, AVX2, AVX-512, and AVX10 SIMD instructions (Source: Intel)<\/figcaption><\/figure>\n<p>Arm processors provide the NEON extension with a width of 128 bits, and with the ARMv9 version of the instruction set, the SVE and SVE2 extensions were additionally standardized, which allow processors to have varying register widths (from 128 up to 2048 bits, in theory) while maintaining code compatibility\u2014though this adds extra complexity to the code. RISC-V processors recently introduced the similarly conceived RVV extension.<\/p>\n<p>Today, so-called matrix extensions are also beginning to appear, which are conceptually similar to SIMD, but perform instructions with an even larger number of operands at once, over entire matrices of values. These extensions in x86 processors are AMX (first featured in 4th generation Intel Xeon Scalable processors, 2022) and in the future the ACE extension will be added (which is expected to appear, for example, in AMD&#8217;s Zen 7 architecture processors in 2028). Arm processors have the SME matrix extension.<\/p>\n<p><em><strong>The article continues on the next page&#8230;<\/strong><\/em><\/p>\n<p><script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script>\n<!-- responsive -->\n<ins class=\"adsbygoogle\"\n     style=\"display:block;background-color:transparent\"\n     data-ad-client=\"ca-pub-8150419924824893\"\n     data-ad-slot=\"6522017574\"\n     data-ad-format=\"auto\"><\/ins>\n<script>\n(adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n&#10240;<\/p>\n<p><!--nextpage-->The processor, also referred to as the central processing unit (CPU), is the most fundamental and the most important part of a computer. It is the part that executes all tasks (instructions) that are fed to the computer through program code. At the same time, peripheral devices, RAM and storage (hard drives, SSDs, oreven tape in the past) are connected to it in various ways. It is therefore truly the central element of a computer.<!--more--><\/p>\n<p>Today&#8217;s processors are extremely complex and sophisticated: the truly in-depth details of their architectures are entirely beyond the scope of this article, but we will try to give some insight into the features of modern advanced CPUs and how they work.<\/p>\n<h2 class=\"western\">Elements of a core<\/h2>\n<p>The structure of processor core architectures is very complex and also often varies. The main elements of a core are divided into the so-called frontend and backend. The <b>frontend<\/b> includes the first-level instruction cache (code), which is the primary place in the processor where program code is held during use. The processor fetches this code by instructions or by a block of a certain number of bytes, decodes individual instructions, which means it determines which instruction it is, and then issues it for further processing to the backend.<\/p>\n<p>Modern processors often have an additional cache (MicroOP or \u00b5OP cache) that stores decoded instructions for later use without having to be decoded again.<\/p>\n<p>The <b>backend<\/b> is the part of the processor that contains the units for executing instructions. These are mainly arithmetic logic units (<b>ALU<\/b>), which execute most of the general purpose instructions of the instruction set. Alongside them, the core also contains so-called <b>Load\/Store<\/b> units. These serve to read data from memory (<i>load<\/i>) or write data to memory (<i>store<\/i>), and may support both or either types of operations. In addition to these units, there may be others present: for example, separate units solely for processing branch and jump operations.<\/p>\n<p>Load\/Store units do not work directly with operating memory; they are first connected to the first-level data cache and then the second-level cache (and then the third), through which data eventually reaches RAM. The first and second-level caches for data are therefore closely associated with the Load\/Store units. These are also sometimes referred to as <b>AGU<\/b>, which refers to the function of generating the target address (<i>Address Generation Unit<\/i>) for memory operations.<\/p>\n<p>An important part of the core is the <strong>registers<\/strong>, which are closely connected to the ALU and Load\/Store units. Registers are sections of special SRAM-type memory directly in the core, into which operands are loaded from memory for processing by instructions, and from which data can then be loaded back into memory.<\/p>\n<p>FPU (x87) and SIMD instructions have their own sets of registers and their own execution units, to which the SIMD and x87 registers are connected. These are essentially also ALUs, but ones capable of working with floating-point operands as well as with the contents of SIMD registers, consisting of a larger number of values at once\u2014see the previous chapter.<\/p>\n<figure id=\"attachment_279546\" aria-describedby=\"caption-attachment-279546\" style=\"width: 905px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-jadra-Zen-5-Frontend-backend.png\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-279546 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-jadra-Zen-5-Frontend-backend.png\" alt=\"Simplified diagram of AMD's Zen 5 core (Source: AMD)\" width=\"905\" height=\"699\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-jadra-Zen-5-Frontend-backend.png 905w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-jadra-Zen-5-Frontend-backend-300x232.png 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Schema-jadra-Zen-5-Frontend-backend-768x593.png 768w\" sizes=\"auto, (max-width: 905px) 100vw, 905px\" \/><\/a><figcaption id=\"caption-attachment-279546\" class=\"wp-caption-text\">Simplified diagram of AMD&#8217;s Zen 5 core (Source: AMD)<\/figcaption><\/figure>\n<h2 class=\"western\">Optimizing program execution<\/h2>\n<p>The original historical concept of a processor is that it processes instructions in the order in which they come in the program sequence, one after another, having to wait for the previous instruction to complete and write its results before starting the next. This is so-called &#8220;in-order&#8221; execution. However, respecting this natural structure of the program would significantly limit performance and processing speed. For example, because some operations (like division) take processors many cycles to finish. But mainly because when processing programs, idle periods arise quite frequently. The most common source of these is that the processor does not have the data from operating memory available that the next instruction needs to work with, and is waiting for it to arrive from memory into the cache and then into the working registers.<\/p>\n<p>To improve performance (to increase the number of instructions processed per unit of time, for example per cycle or per 1 MHz of frequency\u2014often referred to as &#8220;<strong>IPC<\/strong>,&#8221; which originally stands for <i>instructions per cycle<\/i>), it is necessary to execute instructions faster and more sophisticatedly.<\/p>\n<h3 class=\"western\">Pipelining<\/h3>\n<p>A technique used practically universally today is to divide instruction processing into several different steps (stages) that form a pipeline, with each stage performing as much work as can be done in one cycle of the clock signal. Instructions of a program pass through this pipeline sequentially so that when one completes one stage (N), it moves to the next (N+1), and the next instruction enters the execution stage N.<\/p>\n<p>With this processing method, the processor processes several instructions at once, their processing overlapping and each subsequent one being one cycle behind. Pipelining allowed a significant increase in CPU frequencies because the amount of work that the circuits had to perform in one clock cycle was reduced.<\/p>\n<p>To illustrate, common pipeline stages in the first RISC processors using this principle were these, forming the so-called classic five-stage RISC pipeline:<\/p>\n<ol>\n<li>Fetching the instruction from the first-level instruction cache\u00a0as a sequence of bits in which it is written in the program<\/li>\n<li>Decoding the instruction, where the processor determines from the instruction bits which operation it is and which registers to use, which are then read for the next stage<\/li>\n<li>Execution of the instruction, i.e., the actual arithmetic-logic operation performed in the ALU<\/li>\n<li>Memory access, if needed<\/li>\n<li>Writing the results back to registers<\/li>\n<\/ol>\n<p>Modern processors, however, tend to have longer pipelines with a larger number of stages, into which these phases are further subdivided. A larger number of stages, each doing less work, allows the processor core to achieve a higher frequency.<\/p>\n<h3 class=\"western\">Branch prediction and prefetch<\/h3>\n<p>The fact that instructions begin to execute not when the previous instructions are complete, but immediately after the previous ones have only started executing, has both performance benefits and its drawbacks. A consequence is, for example, that if a program encounters a branch instruction, it may not yet be clear which direction the execution flow will take, because, for example, an IF operation depends on a value that is yet to be provided by an instruction still being processed.<\/p>\n<p>To avoid the processor having to wait, so-called branch predictors were developed. These attempt to predict which direction a branch or similar operation in the code will take, based on, for example, the program&#8217;s previous behavior (which works well for code loops), but also on recognizing other, more complex patterns. When the processor encounters a branch instruction, the branch predictor provides a prediction (speculation) of which direction the program will likely take (for example, whether it will jump to another address or continue without a jump), allowing processing to continue immediately.<\/p>\n<p>The disadvantage is that if it turns out the branch prediction was incorrect once previous instructions finally complete, the processor must discard all subsequent instructions and results produced after the speculation and roll back. This requires complex logic and rigorous validation of correct operation. Every incorrectly speculated branch degrades performance, and the penalty is greater the more pipeline stages the processor has\u2014more instructions typically have to be discarded. Improving branch predictors is therefore one of the most important parts of processor improvements, and each new generation of CPU cores strives to improve predictor capabilities by lowering the misprediction rate.<\/p>\n<p>A similar problem and performance limitation as that involving branch predictors is addressed by the prefetch technique. Here, the problem is waiting for data from operating memory, which is relatively slow compared to the CPU and can take tens to hundreds of cycles to deliver data requested by the program being processed in the CPU. To operate at high performance, the processor must therefore request data from memory many cycles before it needs it.<\/p>\n<p>Prefetching consists precisely of estimating in advance which data the processor will need and preloading it into the second and first-level caches, so that the processor finds it there (which is referred to as cache hit) and does not have to wait for delivery from RAM. Just as with branch predictors, the abilities of prefetch to identify patterns in memory access and preload data accordingly are constantly being improved. This technique is also critical for improving CPU performance.<\/p>\n<h3 class=\"western\">Superscalar processors<\/h3>\n<p>After processors implemented pipelining, the next step in improving performance was parallel instruction processing. As mentioned, in a program&#8217;s code, instructions follow one another, but it is not true that they always depend on the previous one (in the sense that the result of the first is one of the inputs of the second, so it must wait for it). The inputs of the current instruction can be data that was prepared by instructions further in the past. Then it is possible to process this instruction simultaneously with the one preceding it.<\/p>\n<figure id=\"attachment_215340\" aria-describedby=\"caption-attachment-215340\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-215340 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka-1024x680.jpg\" alt=\"The first x86 processor to use the superscalar principle was the original Pentium from 1993 (Source: Intel)\" width=\"640\" height=\"425\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka-1024x680.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka-300x199.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka-768x510.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka-600x398.jpg 600w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka-872x579.jpg 872w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2024\/12\/Intel-Pentium-upoutavka.jpg 1536w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-215340\" class=\"wp-caption-text\">The first x86 processor to use the superscalar principle was the original Pentium from 1993 (Source: Intel)<\/figcaption><\/figure>\n<p>Superscalar processors take advantage of this and have multiple parallel units in the core (ALUs, FPU pipelines, Load\/Store units). The more parallel units of one type there are in the core, the more instructions that are not dependent on each other can be processed in one cycle, provided the opportunity arises.<\/p>\n<h3 class=\"western\">In-Order and Out-of-Order execution<\/h3>\n<p>When combining pipelining and superscalar architecture, the presence of dependencies between instructions quickly becomes a limit on how often parallel units can be used simultaneously. The next step in improving performance (IPC) is the transition from strictly in-order execution to so-called out-of-order execution, which means instructions can be executed ahead of time and in a different order than what is their order in the code. This is a technique that significantly improves performance, but also increases the complexity of processors and the difficulty of verifying their correct behavior and eliminating logic errors.<\/p>\n<p>In out-of-order program execution, the processor is not bound by the order of instructions, only by their actual dependencies. If the processor has free execution units for the current cycle, it can issue not only the next instruction in line for execution, but also other instructions that follow later in the program\u2014provided they do not depend on the result of any yet-unfinished instruction. An out-of-order processor always analyzes a certain &#8220;window&#8221; of the program code from which it can &#8220;pick out&#8221; instructions ahead for immediate execution, allowing the remaining dependent instructions to be processed faster once their inputs are ready. The original order of program operations is then restored during the writing of results back (referred to as <i>retire<\/i> phase).<\/p>\n<figure id=\"attachment_279547\" aria-describedby=\"caption-attachment-279547\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Intel-Pentium-Pro-orig.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-279547 size-full\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Intel-Pentium-Pro-orig.jpg\" alt=\"Pentium Pro: A breakthrough Intel processor from 1995 that demonstrated that it was possible to design a successful x86 CPU based on out-of-order execution (Source: Intel)\" width=\"640\" height=\"480\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Intel-Pentium-Pro-orig.jpg 640w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Intel-Pentium-Pro-orig-300x225.jpg 300w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-279547\" class=\"wp-caption-text\">Pentium Pro: A breakthrough Intel processor from 1995 that demonstrated that it was possible to design a successful x86 CPU based on out-of-order execution. The second chip on the right is an external SRAM forming L2 cache (Source: Intel)<\/figcaption><\/figure>\n<p>Using out-of-order execution again increases the number of instructions the processor can execute per cycle, and thus performance. Out-of-order execution allows more efficient use of the execution units available to the processor core, as they will less often stay idle waiting for an instruction to execute.<\/p>\n<p>The success of this technique depends on the size of the program &#8220;window&#8221; that the CPU sees, within which it can find instructions that can be executed immediately. Out-of-order processors use a queue or buffer typically called a <strong>Re-Order Buffer<\/strong> (ROB). This has a certain number of entries within which out-of-order instruction execution can be performed. Initially, it might have been only tens of entries, but in current processors, the depth can be up to several hundred entries. This then provides significantly better opportunities to execute instructions optimally out of order and utilize as many parallel units simultaneously as possible. Some of today&#8217;s processors can thus have 8 or more parallel ALUs and additional Load\/Store units.<\/p>\n<p>Out-of-order processors also have other queues with a similar purpose. For example, Load\/Store units use a queue for load operations (reading data from memory), within which operations can also be executed out of order, and similarly, there is a queue for store operations (writing data to memory).<\/p>\n<figure id=\"attachment_279548\" aria-describedby=\"caption-attachment-279548\" style=\"width: 640px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-scaled.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-279548 size-large\" src=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-1024x683.jpg\" alt=\"The K5 processor was AMD's first original x86 architecture to execute instructions out of order (and also its first x86 superscalar core) (Photo: Fritzchens Fritz)\" width=\"640\" height=\"427\" srcset=\"https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-1024x683.jpg 1024w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-300x200.jpg 300w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-253x168.jpg 253w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-768x512.jpg 768w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-1536x1024.jpg 1536w, https:\/\/www.hwcooling.net\/wp-content\/uploads\/2026\/07\/Procesor-K5-byl-prvni-vlastni-architekturou-vykonavajici-instrukce-mimo-poradi-od-AMD-2048x1365.jpg 2048w\" sizes=\"auto, (max-width: 640px) 100vw, 640px\" \/><\/a><figcaption id=\"caption-attachment-279548\" class=\"wp-caption-text\">The K5 processor was AMD&#8217;s first original x86 architecture to execute instructions out of order (and also its first x86 superscalar core) (Photo: Fritzchens Fritz)<\/figcaption><\/figure>\n<p>Modern processors strive to continuously improve single-threaded performance (which is then multiplied into multi-threaded performance by multiple cores). The means to this end is the diligent pursuit of small cumulative improvements using all these techniques simultaneously: that is, increasing the number of parallel units in the processor, deepening the Re-Order Buffer and other queues used for out-of-order instruction execution, and improving prefetch and branch prediction. All of this can incrementally increase the core&#8217;s IPC (performance per 1 MHz). At the same time, processor architects must optimize the number of pipeline stages and the amount of work done by individual stages to allow the processor to achieve the best possible frequency.<\/p>\n<p>Neither maximum frequency nor maximum IPC alone is sufficient for top-tier performance. Performance is given by the product of frequency and IPC, so for high performance, processors must utilize both of these sources in some combination. Many other techniques are also employed within the processor architecture that contribute either to increasing frequency or to improving IPC, and which cannot be easily listed or described in one place. Their combination makes the modern microprocessors some of the most complex mechanisms in the world. Their fast and, above all, correct and reliable operation without unforeseen deviations from expected behavior is, without exaggeration, a marvel of technology.<\/p>\n<div style=\"margin: 5px 5px 15px 5px; padding: 5px; border: 1px dashed #549AFF; background: #f4f8fe;\"><strong>Expand the content in the comments:<\/strong> The article certainly does not include everything you consider important. However, you can expand this knowledge by posting a comment (or multiple comments) in the discussion below.<\/div>\n<p style=\"text-align: right;\"><em>English translation and edit by Jozef Dud\u00e1\u0161<\/em><\/p>\n<p><script async src=\"\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js\"><\/script>\n<!-- responsive -->\n<ins class=\"adsbygoogle\"\n     style=\"display:block;background-color:transparent\"\n     data-ad-client=\"ca-pub-8150419924824893\"\n     data-ad-slot=\"6522017574\"\n     data-ad-format=\"auto\"><\/ins>\n<script>\n(adsbygoogle = window.adsbygoogle || []).push({});\n<\/script><br \/>\n&#10240;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The processor, also referred to as the central processing unit (CPU), is the most fundamental and the most important part of a computer. It is the part that executes all tasks (instructions) that are fed to the computer through program code. At the same time, peripheral devices, RAM and storage (hard drives, SSDs, oreven tape [&hellip;]<\/p>\n","protected":false},"author":26,"featured_media":202579,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[770,542],"tags":[279,280],"class_list":["post-279666","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-analysis","category-processors","tag-procesory-en","tag-processors"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v24.9 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>How Does a Processor Work? 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