{"id":282629,"date":"2026-10-29T18:00:05","date_gmt":"2026-10-29T17:00:05","guid":{"rendered":"https:\/\/www.hwcooling.net\/?p=282629\/"},"modified":"2026-10-29T19:37:33","modified_gmt":"2026-10-29T18:37:33","slug":"rhea2-mobius100-details-of-second-generation-eu-cpus","status":"publish","type":"post","link":"https:\/\/www.hwcooling.net\/en\/rhea2-mobius100-details-of-second-generation-eu-cpus\/","title":{"rendered":"Rhea2 & Mobius100: Details of Second-Generation EU CPUs"},"content":{"rendered":"

We have an update on developments in the European CPU project. We recently reported that deliveries of the first generation of these server CPUs, Rhea1, have begun<\/a>, after a considerable delay. Now we have more details on the follow-up generation, which SiPearl is currently developing. It could be significantly better and more competitive\u2014provided that it arrives on time this time and is not again delayed by several years.<\/p>\n

Rhea1 processors still use the Neoverse-V1 architecture, which was Arm\u2019s first HPC architecture for servers, and are manufactured on a 6nm process. Fortunately, SiPearl Rhea2 is not a similarly dated design, just one generation newer. It should be a significant jump to roughly the same technology level as represented by Amazon\u2019s current Arm processors, the Graviton5<\/a>. The CPU will be manufactured on TSMC\u2019s 3nm process (N3P<\/strong>) and will be chiplet-based.<\/p>\n

Rhea2 is to consist of two 3nm chiplets with CPU cores and an IO chiplet, which will probably be manufactured on a different, older process (possibly 6nm or 4nm, but that has not been stated). The architecture is again licensed from Arm, with UCIe-2.0 used for interconnect logic, while the CPU cores will utilise the Neoverse-V3<\/strong> architecture, as in the Graviton5.<\/p>\n

Each of the CPU chiplets is to physically contain 70 cores, so the theoretical maximum configuration is 140 cores. It is unclear whether such CPUs will be sold; for yield reasons, the mass-produced production model will probably have some of the cores disabled. Currently, the plan is for the Alice Recoque supercomputer, which is planned to use these processors for part of its cabinets, to use a 128-core configuration.<\/p>\n

The processors\u2019 IO chiplet will contain a controller for DDR5 memory, including support for multi-rank MRDIMM modules at DDR5-12800<\/strong> speeds. With an eight-channel controller, that would provide a theoretical RAM bandwidth of up to 819.2 GB\/s. However, we do not yet know the number of memory controller channels. We also do not know how many PCIe lanes the Rhea2 processor will provide for connectivity. It is promised to support PCI Express 6.0<\/strong>, however.<\/p>\n

\"\"<\/a>
Amazon Graviton4 (Author: Amazon\/AWS)<\/figcaption><\/figure>\n

Overall, the Rhea2 processor would thus be a fully modern server CPU solution today, with an architecture and manufacturing technology comparable to the Graviton5 (although it remains to be seen whether SiPearl will be able to reach the same clock speeds), except that the Graviton5 has 192 cores, significantly more. However, the important matter here is that Rhea2 will arrive significantly later. Samples of the chiplet with the cores are to be ready in roughly a year form now (the end of year 2027, reportedly), and of the entire processor will only sample in mid-2028. It can thus be said that the Rhea2 processor will arrive roughly two to three years after the Graviton5.<\/p>\n

That will still represent quite a lag, but it should no longer prove as fatal as with Rhea1. There is great demand for processors in today\u2019s market, and Intel has no trouble selling\u00a0even old 7nm Xeon processors, probably mainly the 2023 5th generation Xeon Scalable \u201cEmerald Rapids\u201d modely with a maximum of 64 cores<\/a>. Emerald Rapids processors were a significant improvement over the very problematic Sapphire Rapids generation, but even when new they were considerably behind state-of-the-art server chips (especially AMD\u2019s Epyc).<\/p>\n

This shows that the server market has plenty of use for products one or even two generations older (if not even older) than the current day’s best products, and if that situation persists, Rhea2 processors could be fairly viable in market in year 2028. If development goes well, the factors hampering their adoption may stem more from being produced by a smaller less proven company without established relationships with server vendors and service providers than from performance and efficiency. In any case, with a bit of luck, SiPearl could significantly cut the gap between its products and the leading server CPUs from the established vendors. If that succeeds, the entire European CPU project might then look more promising in two years from now int than it does today when looking at the Rhea1 chip.<\/p>\n

Updated: Rhea2, a.k.a. Mobius100<\/em><\/h3>\n

According to a press release from SiPearl, Rhea2 processors will be developed in cooperation with another company, Alcor Micro, which belongs to the French multinational Egis Group (Alcor Micro, however, is based in Taiwan). In the press release, their jointly developed processors are also designated Mobius100, and it is stated that Rhea2 will be built on their architecture.<\/em><\/p>\n

What exactly the relationship between these two CPUs will be remains to be seen. In theory, they could, for example, share CPU chiplets but have their own IO chiplet, or one may be a modified version of the other\u2019s design. Alcor Micro announced the Mobius100 processors a year ago<\/a>.<\/em><\/p>\n

Sources: Hardwareluxx<\/a>, SiPearl<\/a><\/em><\/p>\n

English translation and edit by Jozef Dud\u00e1\u0161<\/em><\/p>\n