{"id":82721,"date":"2022-01-05T14:30:53","date_gmt":"2022-01-05T13:30:53","guid":{"rendered":"https:\/\/www.hwcooling.net\/?p=82721\/"},"modified":"2022-02-24T19:25:52","modified_gmt":"2022-02-24T18:25:52","slug":"core-i5-12400-with-ddr4-test-meet-the-fresh-bestseller","status":"publish","type":"post","link":"https:\/\/www.hwcooling.net\/en\/core-i5-12400-with-ddr4-test-meet-the-fresh-bestseller\/","title":{"rendered":"Core i5-12400 with DDR4 test: Meet the fresh bestseller"},"content":{"rendered":"\n

The more efficient Alder Lake processors with TDP\/PL1 35\u201365 W are out. We are, of course, ready, and for a perfect overview we have complete tests of the Core i5-12400, i.e. the successor of the most popular models of the past generations. You can compare this processor in all aspects not only with them, but also with the Ryzen 5 5600X . It looks like this processor will sell like hot cakes.<\/p>\n

Intel Core i5-12400 in detail<\/h2>\n

The current offer is now rounded out by 22 new Intel Alder Lake processors with a closed multiplier and no K in the designation. They range from Celerons to Core i9s (including the T models with TDP lowered to 35W), but most are Core i5s. This class traditionally starts with models with 400 in the designation \u2013 12400 and 12400F (without iGPU). We will spend a good while on the Core i5-12400 within this article. This is the successor of processors that enjoyed high popularity among users in earlier generations (Rocket, but especially Comet Lake). This is both because of the favorable price\/performance ratio, but also with high efficiency (performance per unit of power draw). As is the case with all Intel Alder Lake processors, they are built on the new Intel 7 manufacturing process, which should be a comparable alternative to TSMC’s 7 nm process (AMD processors).<\/p>\n

The Core i5-12400(F), unlike the Core i9 and Core i9 Alder Lake, no longer use the efficient (E) Golden Cove cores. But there are two variants of the processors, one has them deactivated and the other has none physically within the chip at all. This is a pretty big topic with Core i5 Alder Lake. It’s always a 6-core processor with twelve threads (i.e. HyperThreading support), but you can come across two different versions. One has native, 6-core silicon without the small E cores and is a 6+0 configuration. The internal designation for this stepping is “H0”.<\/p>\n

But Intel is also capitalizing on failed pieces of silicon with various manufacturing defects that don’t meet the requirements for higher-end models. These processors have a chip with 8+8 cores. The internal stepping here is “C0”. This variant also has no active E cores, although they are physically present. This can translate to slightly higher latency on the ring bus due to the extra hidden “stops” for the inactive cores and the two E-core clusters. However, the performance impact in real applications is negligible. The small advantage of these processors will lie in a larger core with better heat dissipation and probably with soldered IHS. But even that won’t translate much in this power class and the temperatures will be very similar.<\/p>\n

\"\"<\/a><\/p>\n

While there is a bigger chip and TIM with better heat conducting properties, the Core i5-12400 with bigger chips have higher power draw (the biggest percentage difference will probably be off load) and it will eventually balance out give or take. I guess you could say that you don’t have to regret whatever you get in the shopping lottery, one way or the other. We have, for testing purposes, a processor with stepping C0 (i.e. a chip with 8 P and 8 E cores, of which, of course, a large part is turned off). Core i5s with a native 6-core chip have stepping “H0”. But the main identifying feature for you is the S-Spec code, which is a 5-digit alphanumeric designation on the metal heat spreader. With C0, it’s SRL4V. In addition, the underside of the processor is also different, specifically the layout and number of SMDs in the rectangular space between the contacts. If the underside looks the same as the Core i9-12900K, then it is an 8+8\/C0 processor. The distinguishing feature is the presence of two larger blocks with SMDs in a 3\u00d73 matrix.<\/p>\n

We do not know the S-Spec code for the processor with the smaller chip. And the area size of these Core i5s is also unknown. But you can ask the vendor for the S-Spec code and find out which variant it is. It’s not on the box printing, but it’s visible even without breaking the sticker\/seal. Traditionally through the window on the side that reveals the top of the IHS. If an online store has the processor in stock and wants to be helpful, they will be able to read the S-Spec code for you. Based on that, you will be able to tell which of the two possible variations it is. At least for now, from the start. It’s possible, in fact, that over time these codes may change if Intel switches to a new stepping or makes some minor revision. S-Spec codes for a particular processor model are not constant.<\/p>\n

\"\"<\/a>\u00a0 \u00a0\"\"<\/a><\/p>\n

Core i5-12400(F) are slightly more expensive than the previous Core i5-11400(F) Rocket Lake<\/a> models, but again come out significantly cheaper than the Ryzen 5 5600X<\/a>. The added value of the non-F Core i5 model is in the presence of the iGPU. This is the Intel UHD 730 with 24 EU. But AMD also has some aces up its sleeve. Although Core i5-12400(F) lists a lower PL2 for the CPU than Core i5-11400(F) – 117 vs. 154 W, without limitations the R5 5600X with 88 W PPT will still probably be quite a bit more power efficient. But the key here is the interplay of power draw with compute or gaming performance. We don’t need to theorize about this anymore, you’ll learn everything, including efficiency information, from the detailed analyses of our tests.<\/p>\n

<\/div>
<\/th><\/th><\/th><\/th><\/th><\/tr><\/thead>
Manufacturer <\/td><\/td>Intel <\/td>Intel <\/td>AMD <\/td><\/tr>
Line <\/td><\/td>Core i5 <\/td>Core i5 <\/td>Ryzen 5 <\/td><\/tr>
SKU <\/td><\/td>12400 <\/td>11400F <\/td>5600X <\/td><\/tr>
Codename <\/td><\/td>Alder Lake <\/td>Rocket Lake <\/td>Vermeer <\/td><\/tr>
CPU microarchitecture <\/td><\/td>Golden Cove (P) <\/td>Cypress Cove <\/td>Zen 3 <\/td><\/tr>
Manufacturing node <\/td><\/td>7 nm <\/td>14 nm <\/td>7 nm + 12 nm <\/td><\/tr>
Socket <\/td><\/td>LGA 1700 <\/td>LGA 1200 <\/td>AM4 <\/td><\/tr>
Launch date <\/td><\/td>01\/04\/2022 <\/td>03\/30\/2021 <\/td>06\/21\/ 2020 <\/td><\/tr>
Launch price <\/td><\/td>192 USD <\/td>157 USD <\/td>299 USD <\/td><\/tr>
Core count <\/td><\/td>6 <\/td>6 <\/td>6 <\/td><\/tr>
Thread count <\/td><\/td>12 <\/td>12 <\/td>12 <\/td><\/tr>
Base frequency <\/td><\/td>2.5 GHz (P) <\/td>2.6 GHz <\/td>3.7 GHz <\/td><\/tr>
Max. Boost (1 core) <\/td><\/td>4.4 GHz (P) <\/td>4.4 GHz <\/td>4.6 GHz (4,65 GHz unofficially) <\/td><\/tr>
Max. boost (all-core) <\/td><\/td>4.0 GHz (P) <\/td>4.2 GHz <\/td>N\/A <\/td><\/tr>
Typ boostu <\/td><\/td>TB 2.0 <\/td>TB 2.0 <\/td>PB 2.0 <\/td><\/tr>
L1i cache <\/td><\/td>32 kB\/core (P) <\/td>32 kB\/core <\/td>32 kB\/core <\/td><\/tr>
L1d cache <\/td><\/td>48 kB\/core (P) <\/td>48 kB\/core <\/td>32 kB\/core <\/td><\/tr>
L2 cache <\/td><\/td>1,25 MB\/core (P) <\/td>512 kB\/core <\/td>512 kB\/core <\/td><\/tr>
L3 cache <\/td><\/td>1\u00d7 18 MB <\/td>1\u00d7 12 MB <\/td>1\u00d7 32 MB <\/td><\/tr>
TDP <\/td><\/td>65 W <\/td>65 W <\/td>65 W <\/td><\/tr>
Max. power draw during boost <\/td><\/td>117 W (PL2) <\/td>154 W (PL2) <\/td>88 W (PPT) <\/td><\/tr>
Overclocking support <\/td><\/td>No <\/td>No <\/td>Yes <\/td><\/tr>
Memory (RAM) support <\/td><\/td>DDR5-4800\/DDR4-3200 <\/td>DDR4-3200 <\/td>DDR4-3200 <\/td><\/tr>
Memory channel count <\/td><\/td>2\u00d7 64 bit <\/td>2\u00d7 64 bit <\/td>2\u00d7 64 bit <\/td><\/tr>
RAM bandwidth <\/td><\/td>76.8 GB\/s or 51.2 GB\/s (DDR4) <\/td>51.2 GB\/s <\/td>51.2 GB\/s <\/td><\/tr>
ECC RAM support <\/td><\/td>No <\/td>Yes <\/td>Yes but unofficial <\/td><\/tr>
PCI Express support <\/td><\/td>5.0\/4.0 <\/td>4.0 <\/td>4.0 <\/td><\/tr>
PCI Express lanes <\/td><\/td>\u00d716 (5.0) + \u00d74 (4.0) <\/td>\u00d716 + \u00d74 <\/td>\u00d716 + \u00d74 <\/td><\/tr>
Chipset downlink <\/td><\/td>DMI 4.0 \u00d78 <\/td>DMI 3.0 \u00d78 <\/td>PCIe 4.0 \u00d74 <\/td><\/tr>
Chipset downlink bandwidth <\/td><\/td>16.0 GB\/s duplex <\/td>8.0 GB\/s duplex <\/td>8.0 GB\/s duplex <\/td><\/tr>
BCLK <\/td><\/td>100 MHz <\/td>100 MHz <\/td>100 MHz <\/td><\/tr>
Die size <\/td><\/td>~209 or ~160 mm\u00b2 (depending on variant) <\/td>276.4 mm\u00b2 <\/td>1\u00d7 80.7 mm\u00b2 + 125 mm\u00b2 <\/td><\/tr>
Transistor count <\/td><\/td>? bn. <\/td>? bn. <\/td>4.15 + 2.09 bn. <\/td><\/tr>
TIM used under IHS <\/td><\/td>Solder * <\/td>Solder <\/td>Solder <\/td><\/tr>
Boxed cooler in package <\/td><\/td>Intel Laminar RM1 <\/td>top-flow with cooper core <\/td>AMD Wraith Stealth <\/td><\/tr>
Instruction set extensions <\/td><\/td>SSE4.2, AVX2, FMA, SHA, VNNI (256-bit), GNA 2.0, VAES (256-bit) <\/td>SSE4.2, AVX2, FMA, AVX-512, SHA, VNNI, GNA 2.0 <\/td>SSE4.2, AVX2, FMA, SHA, VAES <\/td><\/tr>
Virtualization <\/td><\/td>VT-x, VT-d, EPT <\/td>VT-x, VT-d, EPT <\/td>AMD-V, IOMMU, NPT <\/td><\/tr>
Integrated GPU <\/td><\/td>UHD 730 <\/td>N\/A <\/td>N\/A <\/td><\/tr>
GPU architecture <\/td><\/td>Xe LP (Gen. 12) <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
GPU: shader count <\/td><\/td>24 <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
GPU: TMU count <\/td><\/td>12 <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
GPU: ROP count <\/td><\/td>8 <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
GPU frequency <\/td><\/td>350\u20131550 MHz <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
Display outputs <\/td><\/td>DP 1.4a, HDMI 2.0b <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
Max. resolution <\/td><\/td>5120 \u00d7 3200 px (60 Hz) <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
HW video decode <\/td><\/td>AV1, HEVC, VP9 <\/td>\u2013 <\/td>\u2013 <\/td><\/tr>
HW video encode <\/td><\/td>HEVC, VP9 <\/td>\u2013 <\/td>\u2013 <\/td><\/tr><\/tbody><\/table><\/div>Wordpress Table Plugin<\/a><\/p>\n
* This refers to a processor with a larger, natively 8+8-core chip. A pure 6-core may (or may not) use a thermally conductive paste as the thermal interface between the silicon case and the IHS. We’ll update this information when a delid appears somewhere.<\/strong><\/h6>\n