Introduction: Desktop Zen 5 fits in the same die area as Zen 4
It’s roughly two weeks until AMD releases processors with the new Zen 5 architecture. This week, we finally got proper details on these CPUs’ architecture, which AMD revealed at the Tech Day event. So, we can now break down the changes the company has made to the core, compared to Zen 4 – and they’re pretty extensive, probably more so than they seemed in June. And AMD also reiterated its promise of a 16% increase in IPC for these CPUs.
We have originally published our analysis of the AMD Zen 5 architecture on 19th of July. However, AMD has unusually disclosed the technical details in two steps, initially during the Tech Day event but then following with more thorough deep dive last week in a further press briefing which we had the opportunity to attend. That’s why we are republishing the write-up on Zen 5 again, this time expanded and revised with the newly available data on the new core. It doesn’t change our conclusion, in fact the new disclosures show yet more areas that AMD has reworked when developing the architecture.
Big upgrades to the core without changing the chip(let) area?
AMD has confirmed that Zen 5 uses TSMC’s 4nm N4P node for both the desktop Ryzen 9000 (specifically for its CPU chiplets) and the mobile Ryzen AI 300, or “Strix Point” APU. Strix Point is a relatively large chip with a die area of 232.5 mm² (Phoenix and Hawk Point predecessors based on Zen 4 architecture have a die area of just178 mm²), which implies increased manufacturing costs.
Surprisingly, this isn’t true for the desktop version: the CPU chiplet with eight Zen 5 cores for the Ryzen 9000s hasn’t gotten any bigger compared to the Ryzen 7000 chiplet. It reportedly has a die area of 70.6 mm², while the 5nm Zen 4 chiplet is listed at 71 mm². The IO chiplet is still the same, a 6nm die with a die area of 122 mm². So it seems that the Zen 5 core itself hasn’t gotten much bigger, or AMD has only let it bloat by as much as the architects managed to save elsewhere by optimizing the design and using the slightly better 4nm node. This will probably further widen the already notable gap between the core sizes of AMD and Intel, whose P-Cores (performance cores) have a much larger die area than the cores of the AMD Zen lineage.
In interviews at Tech Day, one of the lead engineers (or now engineering team managers), Mike Clark, confirmed that Zen 5 is a new core in the Zen line of architectures that largely establishes a new foundation. So was Zen 3, but Zen 5 is is probably a case of a more profound change, as the long-maintained foundation built around a core with four decoders and four ALUs that held from Zen 1 through Zen 4 has been abandoned. Instead, Zen 5 brings a new broader foundation for future development (though it might not necessarily be used as long as the previous one).
Some of the investment in this core reorganization may really only bring back dividend in the follow-up future generations. It is possible that in some respects, Zen 5 might mainly be setting the stage, since the company’s resources have been focused on successfully creating this foundation and build a functional first generation on it, rather than including all the potential enhancements that could be added right away at this starting point. As an example, Mike Clark revealed that Zen 5 does not currently have the NOP instruction fusion capability that previous cores contain (allowing up to four NOPs to occupy only one “spot” in the processor pipeline and in RoB). Allegedly this feature would have slightly less benefit than it had in older, narrower cores, so the decision was made to leave its reintroduction for later.
The article continues on the next page.
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- Contents
- Introduction: Desktop Zen 5 fits in the same die area as Zen 4
- Frontend: The biggest new feature of the core
- Execution units upgrade I: 6× ALU
- Execution units upgrade II: Full-speed AVX-512
- Higher performance and finally larger L1 cache; on SMT
- The greatest architectural achievement since the transition to Zen architecture (Conclusion)
