AMD Strix Point: 12 cores, 1024 RDNA 3.5 architecture shaders

ES Ryzen 8050 in HWiNFO64

The year 2024 is slowly approaching, in which Zen 5 based AMD Ryzen 8000 processors should come out. Now, a HWiNFO leak has hit the internet, apparently taken on a sample of such a processor, which slipped out from AMD or some board manufacturer, or that someone at those companies screencapped. Thanks to this we have a look at some of the specs of a Strix Point APU, i.e. the Ryzen 8050 for laptops with integrated RDNA 3.5 graphics.

This information appeared on Performance Databases and shows an engineering sample of a Ryzen 8050 processor (this nomenclature is based on the CPU having the Zen 5 architecture, the final model will be called, for example, Ryzen 9 8950H), codenamed “Strix Point 1”. According to the designation STX1-A0 it is an early sample.

The processor has 45W TDP according to the detection, so it will probably be a HS or H series model, but in any case it is an APU for laptops in a BGA package (FP8), running in a development board with 32GB LPDDR5 or LPDDR5X memory. A desktop version for the AM5 socket is probably coming too, but it may come out much later after the mobile one (given how right now, we’re still waiting in vain for the desktop Ryzen 7000 “Phoenix”).

What does the leak reveal about the parameters? If it’s authentic, it proves that Strix Point is a 12-core. According to the detection, it is supposed to have four Zen 5 cores and eight Zen 5c cores (which will probably again be an architecture with the same IPC and features as Zen 5, but with lower clock speeds due to optimization to reduce the area, like the Zen 4c). Both kinds of cores support SMT, so the whole will provide 24 threads.

HWiNFO shows only 8MB L3 cache, but it is possible that this is not detected correctly and the processor has for example separate 8MB for Zen 5 cores in one CCX and 8MB for Zen 5c cores in the other CCX. The private L2 cache in both kinds of cores still has 1 MB as in Zen 4/4c, but the L1 cache has increased. While Zen 2 to Zen 4 maintained 32 KB for instructions and 32 KB for data, Zen 5 has the L1 for data increased to 48 KB (L1i is still 32KB). This could be quite helpful for IPC.

Instruction support is apparently the same or similar to Zen 4, the processor again supports AVX-512. However, it is possible that the minor instruction extensions that might be added with Zen 5 are simply not yet reported by HWiNFO. Its listing of instruction extensions doesn’t go into full detail (see, for example, the AVX-512 combined into a single entry).

Ryzen 8050 in HWiNFO64 (Source: Performance Databases)

Largest integrated GPU so far

But the program shows something interesting about the integrated GPU of the Strix Point. The graphics core is detected to contain 1024 shaders (16 CUs), which would be AMD’s most powerful integrated GPU to date (only Apple’s big high-end GPUs like those integrated in the M2 Pro and Max have more units). According to HWiNFO, the graphics core should contain 16 ROPs and 64 texture units. Also, 16 Ray Accelerators should be present. According to Twitter leaker Kepler, a configuration with all 8 WGPs (16 CUs) within a single Shader Array is being used.

The detection says that the graphics core uses 512 MB of GDDR6 memory, but this is probably a misdetection. It is likely that the shared memory within the main RAM of the system will still be used.

APU roadmap showing Ryzen 8000 “Strix Point” from Financial Analyst Day 2022 (Source: AMD)

RDNA 3.5

According to earlier reports, the architecture used will be RDNA 3.5, which is an enhanced version of the RDNA 3 architecture now used in Radeon’s RX 7000 generation graphics cards and also in the Ryzen 8040 (“Phoenix”) APUs. It is a hybrid of RDNA 3 and some new IP components that will appear in the next generation RDNA 4. Updated blocks include new scalar ALU in CU blocks that will get FP32 instruction support and also the geometry engine is expected to include several improvements.

RDNA 3.5 also allows a larger number of CUs or WorkGroup Processors to be present in a single Shader Array than before. Also, the ability of CUs to execute two instructions in one cycle (the dual-issue capability introduced in RDNA 3) is said to be improved, which could hopefully enable the feature to provide a larger performance increase than we can see it providing in RDNA 3. In addition to this, RDNA 3.5 is said to have some other minor tweaks (things that may not be as important).

RDNA 3.5 as an improved version of RDNA 3 architecture will be used only in APUs such as Ryzen 8050. According to previous information AMD is not planning any discrete GPUs based on this generation. Big dedicated graphics cards will jump straight to the RDNA 4 generation which will later bring, for example, improved Ray Accelerators for raytracing effects and a new scheduler according to Kepler (but this is probably not the complete list of changes). These new features will not yet be presetn in RDNA 3.5.

RDNA 4 (apparently in dedicated Radeon RX 8000 series GPUs) is said to be coming out in 2024 according to Kepler. But keep in mind that this is probably still tentative, it can’t be ruled out that the release will be delayed and won’t happen until 2025, as it seems to be the case with the GeForce RTX 5000s.

Sources: Performance Databases, VideoCardz, Kepler (1, 2, 3, 4, 5)

English translation and edit by Jozef Dudáš

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