Epyc Siena for low-end server, edge, storage and telecom comes to market
This year, AMD has already released the Epyc 9004 “Genoa”, a 96-core server version of the Zen 4 architecture and even the HPC Genoa-X models equipped with 3D V-Cache. Now they are joined by a separate family – processors codenamed Siena, which are specifically designed for lower power draw and lower cost. They have their own SP6 platform with six-channel memory controller (so the boards should cost less too) and TDPs starting from 70W.
AMD announced the Siena processors in last year’s roadmap and the SP6 socket was also known from leaks. They are now coming to the market under the Epyc 8004 designation, which will distinguish them well from previous generations and from the higher-end Epycs on the SP5 platform with their 12-channel memory. AMD says that the 8004/Siena CPUs complete the fourth-generation Epyc lineup (adding lower price tiers), so the next new CPUs for servers should already be something with the Zen 5 architecture.
The intended use of the 8004 series is to be mainly for cloud services, “edge” servers, storage systems and also for telecom infrastructure, so perhaps they are to partially compete with Intel’s E-Core-based processors such as the Atoms P5900 “Snow Ridge”. And, of course, they are also generally targetting all lower-cost servers.
The Epyc 8004 processors are apparently based on 5nm chiplets with Zen 4c cores (at 16 cores in two CCX blocks per CPU die), the same silicon that is in the cloud-native Epyc 9704 (codenamed Bergamo). The maximum number of chiplets used is four, giving Siena processors up to 64 cores and 128 threads and 128MB of total L3 cache – that’s the configuration of the highest-end models.
On the other hand, Siena uses the same 6nm IO chiplet as Bergamo and Genoa processors, only its I/O functionality is not fully utilized. This is probably a minus for manufacturing costs and maybe even for power efficiency, but the upside is that the once done, validations of DDR5 memory and peripherals for Epyc 9004 will also be valid for Epyc 8004.
Cheaper platform and smaller socket
The processors have the distinct SP6 socket, so it is a separate incompatible platform parallel to Epyc 9004 on the SP5 socket. On the other hand, the simpler socket and connectivity should make boards cheaper. The processors are 58.5 mm × 75.4 mm, the same as the SP3 and Theadripper socket, so coolers will probably be compatible.
SP6 uses a six-channel memory controller with DDR5-4800 support (including ECC) when populating one module per channel, and the specs say the maximum supported RAM capacity is 1.152TB, which is with twelve 96GB modules. It’s unclear whether more RAM will be supported with future higher-capacity modules. According to AMD, the SP6 platform supports basic RDIMM modules, but not the more expensive 3DS RDIMMs that use die stacking for higher capacities.
PCI Express connectivity is also somewhat limited compared to the SP5 platform, but not drastically so. All lanes come from the processor acting as an SoC (without the additional chipset still used by competing Intel Xeon processors to date). Epyc 8004 provides 96 PCI Express 5.0 lanes, which is still decent. 48 of those lines can be used as a coherent CXL 1.1 interface.
The big difference compared to SP5 is that the SP6 platform is limited to single-processor function, it does not support 2S servers. According to AMD, a 2S SP6 platform would not make sense because it could be fully replaced by a single 1S server of the SP5 platform (Epyc 9004 Genoa with 96 and especially Epyc 9704 “Bergamo” with 128 cores).
Lower power draws
And along with the cheaper design, the platform’s power draw is also different and should be fine-tuned for greater power efficiency. The base TDPs of the now listed Epyc 8004 models range from 80 W to 200 W. However, the TDP can be adjusted for the processors (more specifically, for those with the P suffix in the name) and can be reduced from the default 90 W to 70 W for the lowest-power Epyc 8024P model, which has only eight cores and 32 MB of L3 cache. The TDP can be increased as well, with a large number of models allowing you to set it as high as 225 W. The standout is the most powerful 64-core model, the Epyc 8534P, which has a default TDP of 200 W, but can be optionally set from 155 W up to 255 W, which is the highest power draw within the SP6 platform.
Models
There are a total of 12 models – six basic P models for general purpose servers and six PN series models, which will probably be intended mainly for telecommunications or storage applications somewhat closer to the embedded usage. There are six models in both series, one of each core count configuration offered, which are 64, 48, 32, 24, 16 and 8 cores (always with SMT, i.e. twice that many threads).
P models have configurable TDPs (base TDPs range from 90 to 200 W, adjustable from 70–100 W for the octa-core to 155–255 W for the 64-core). These models have an operating temperature range of 0–75 °C. The other half of the models with PN designation use fixed TDPs (which are slightly lower, from 80 to 175 W) which are not adjustable. These models have an extended range of supported temperatures, from -5 °C to +85 °C, the N in the name indicating that these processors are NEBS-friendly, they comply with NEBS (Network Equipment Building System) requirements.
The lower TDP and the use of Zen 4c architecture results in lower clock speeds, as the core is optimized for high transistor density (i.e. small area occupied on the die) instead of high clock speeds. Base clock speeds range from 2.0 to 2.65 GHz; the most powerful 64-core model, the Epyc 8534P, has a base clock speed of 2.3 GHz. Maximum boosts are then 3.0 GHz for most models, and 3.1 GHz for top SKUs.
The Epyc 8004 processors should be immediately available on the market, with official prices going from 409 USD to 4,950 USD for the regular P-series models. PN models with extended operating temperature range cost from 525 USD to 5,450 USD. But as usual, large customers will probably be buying at volume discounts, so this is more of a rough indication.
Sources: AMD, AnandTech, ServeTheHome
English translation and edit by Jozef Dudáš
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