3GHz Arrow Lake-S sample observed on the web
Couple days ago, documents leaked on Arrow Lake-S processors and Generation 800 chipsets – Intel’s next-gen desktop platform with the new LGA 1851 socket, due out in the second half of the year. Besides the things we already analysed, those documents also indicate that Arrow Lake P-cores have only one thread. This has now been confirmed by a log from testing a sample of this CPU. After 22 years, Intel processors are dropping HT.
In those Intel documents that were leaked on Twitter by the leaker with the handle YuuKi_AnS (the same that has presented delidding photos and even die shot of Sapphire Rapids CPU year and a half prior to their launch), there is a description of a sample Arrow Lake processor with 8 big and 16 little cores and a 125W TDP. Unfortunately, the clock speeds are censored, but for the big cores it says: 8 IA Cores/8 threads – which means without HT. The “IA” stands for Intel Architecture and is what Intel used to call its x86 cores in general, in this document it seems to serve as a term distinguishing P-Cores from little cores which are called “Atom cores”.
In the meantime, a trace of Arrow Lake has already appeared on the Internet in a Linux log, apparently coming from a test PC at Intel. It is a Linux boot log taken on an ES sample of an Arrow Lake processor. This listing confirmed that the 8 big cores on Arrow Lake really only amount to 8 threads. The entire processor with 8+16 cores has only 24 threads (“24 CPUs” in the log), while Raptor Lake provides 32 threads in total.
According to the log, the sample was running in a test board (Intel Corporation Arrow Lake Client Platform/MTL-S). Based on the log, the chip reports CPU Family 0x6, Model 0xc6, Stepping 0x0, and was running at 3.0 GHz, which is apparently the case for the big cores; a likely separate clock speed for the little cores is not listed in the log.
In addition to the absence of HT, this log also revealed that Arrow Lake will apparently keep on not supporting AVX-512. This decision is presumably contingent on E-Cores supporting, or in this case non supporting the extension. As InstLatX64 points out, there is a theoretical possibility that these cores do in fact support AVX-512 and HT, but this support is being disabled by the BIOS. For AVX-512 there is perhaps still some hope that this is the explanation, but since the absence of HT is indicated by Intel documents as well, in its case the lack of it is probably due to the hardware itself and HT cannot be enabled in the BIOS.
Rumours that the architectures of the big cores used in the Lunar Lake and Arrow Lake processors will lose HT (or SMT, if you prefer) have been emerging for some time. Looks like they weren’t talking smack and this is really going to be the reality.
Hyper Threading was a feature first introduced in the Netburst architecture, i.e. in the Pentium 4. It wasn’t enabled in the first Willamete core, but the 130nm Northwood chip introduced it to market – the first “Pentium 4 HT” came out in November 2002. Intel will therefore discard HT almost exactly 22 years after it’s introduction. Of course, it is possible that this is only a temporary thing and CPUs will get HT back later. This has already happened once during a architectural transition. Core 2 (which had its evolutionary roots in Pentium III, rather than Pentium 4) did not support Hyper Threading, but the feature was added back by the following Nehalem architecture.
An imbalance between threads?
There’s one particular reason why we find the abandonment of Hyper Threading strnge. For Alder Lake and Raptor Lake, the differences in core performance are roughly such that when using HT and loading both threads of a big core, the performance available on those individual threads is pretty close to the single-threaded performance offered by the (always 1-thread) E-Cores, given how the P-Core’s performance gets split. So even though the CPU is a hybrid architecture, there is still some balance retained when running applications that scale to all threads, thanks to this characteristic.
However, if Arrow Lake loses HT, this will no longer be the case and there will be a significant difference between the performance of P-Core threads and E-Core threads in applications that fully utilize all CPU cores. It is possible that this is not entirely as intended and that Arrow Lake (or rather its big core) originally still counted on having HT. However, there may have been flaws discovered in the architectural implementation that cannot be fixed quickly by simple revisions, so it was decided to just disable the feature for the time being.
These cores are to use a new and possibly significantly rebuilt architecture aimed at substantially higher IPC. Such complex innovations are often associated with an increased amount of errata that engineers have to deal with. For example, the Arrow Lake documents state that engineering samples (which possibly very early silicon), or test boards for them, have the big cores disabled by default for the sake of stability. The given generation of samples seems to have bugs severe enough that the big cores can be optionally enabled for testing purposes, but are disabled by default.
Note: These bugs that forced the P-Cores to be disabled in the leaked samples will obviously be fixed in later revisions, so don’t take it as an indicator of poor quality of Arrow Lake processors. For example, the first samples of Ryzen 1000 silicon produced had a virtually non-functional memory controller, as one of the AMD engineers recently revealed. Basically, this is sometimes a normal part of the bring-up process with early silicon of the very first batches that come out of the factory.
Source: InstLatX64
English translation and edit by Jozef Dudáš
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