Embedded Epyc with Zen 6 architecture revealed in leaked docs
Some time ago, youtuber Moore’s Law Is Dead leaked the first information with AMD’s Zen 6 architecture coming after the yet-to-be-released Zen 5. Now he has another juicy rumor regarding these CPUs, which could come to market in 2026 (late 2025 at best), as he has received documents showing a server and embedded version of them. These designs may however reveal quite a bit about desktop Ryzens with this architecture as well.
Moore’s Law Is Dead showed documents and diagrams related to the next generation Embedded Epyc with Zen 6 architecture. Embedded Epyc is a derivative of AMD server processors, but it exists not only in a socket version (which is basically a server Epyc CPU), but also in a BGA package soldered to the board. However, it uses shared silicon – IO dies shared with regular server dies and the CPU core dies were previously shared with desktop CPUs as well.
32-core chiplet (for servers), PCI Express 6.0
Perhaps the most interesting information is that Zen 6 should bring a new chiplet design and part of that will be an increase in the number of cores in a single CPU chiplet to up to 32 cores – in the server variant, at least. The embedded version of the Zen 6-based Epyc is to be codenamed Venice (like the successful 90nm Athlon 64 processors 20 years earlier), and according to AMD documents, it uses the same IO die as well as the same CPU die (CCD) as the standard server version, which will have the new SP8 socket (this is also a pretty important piece of information – using new socket means servers won’t be upgradeable from Zen 4 or 5 to Zen 6).
The embedded version will also not be compatible with the previous ones. It’s supposed to have two versions. The less powerful version, the Epyc-E Entry in BGA package will contain one IO die and a maximum of two CCDs (chiplets with Zen 6 CPU cores). One CCD has 32 cores, so this version of the processor is expected to have a maximum of 64 cores in a BGA package. One IO die is designed to provide 32 PCIe 5.0 lanes and 16 PCI Express 6.0 lanes. This platform will be the first from AMD to support PCIe 6.0 and it will be interesting to see if this carries over into the desktop version of processors with the Zen 6 architecture.
Tip: PCI Express 6.0 technology released. Double the speed of PCIe 5.0, already 8 GB/s per lane
The memory controller provides four channels and supports DDR5-6400 memory (there is probably some chance of higher speeds, as it says “6400+”) – so the socket and platform will change, even though the time for DDR6 memory has not yet come.
The more powerful Epyc-E Standard version for a socket will use the same SP8 implementation as the standard servers. This version is supposed to have an eight-channel DDR5-6400+ controller and apparently two interconnected IO dies(physically consisting of the same silicon as in the cheaper version). Also, the connectivity will be doubled – 64 PCIe 5.0 lanes and 32 PCIe 6.0 lanes, so the connectivity of the two IO dies will be adding up.
This eight-channel SP8 platform is apparently a lower-cost server platform that is the successor and analogue of the recently released SP6 platform with Epyc 8004 “Siena” processors. So alongside the SP8, there should probably be a more powerful SP7 platform, which will have Epyc 9006 processors, which could have a 12-channel or 16-channel memory controller, more PCIe lanes and support for 2S configurations. This in turn would be the successor to today’s SP5/Epyc 9004 “Genoa” platform. It is quite possible that this SP7 platform will use the same IO dies, but in a higher number of three or four (and almost certainly the same CPU dies). If four IO diesand eight CCDs were used, the resulting processor could have up to 256 cores / 512 threads. However, the sharing of the BGA and SP8 version IO dies with the high-end SP7 platform is not yet confirmed.
Alternative accelerators instead of CPU cores
However, according to the piece of documentation shown by Moore’s Law Is Dead, other sorts of chiplets can be connected to IO dies, not just CPU dies. Instead of one (or more?) CCDs, it should be possible to use alternative silicon. This could theoretically be an integrated FPGA (produced by Xilinx), but the document so far mentions another alternative: the integration of a “NCD” (Network Compute Die) chiplet with SmartNIC or DPU functionality.
AMD bought the Pensando company producing these products some time ago and this NCD chiplet is to use Pensando’s “Salina” IP. A processor so equipped would have integrated acceleration for network tasks, network traffic analysis and data processing, and probably also Ethernet network interfaces. The BGA version of the processor would thus have a maximum of 32 cores in addition to the network part.
Advanced 2.5D packaging?
According to Moore’s Law Is Dead schematics, the chiplets in this generation are finally connected by advanced silicon-bridge packaging, which could reduce the negative effects on performance and power draw that are inflicted by AMD’s current chiplet solution that is based on a common type of packaging, where all chiplet communication goes through thick (and long) wires in a the underlying ordinary glass or organic substrate.
This advanced packaging should then be used to connect the two IO dies as well as to connect the IO dies and CPU dies. Hopefully this will make it to the desktop version as well, where it could again be a major innovation for power efficiency of processors, the biggest since the introduction of the MCM chiplet design in the Ryzen 3000 generation. This would also bring AMD in line with the chiplet/tile design of Sapphire Rapids, Meteor Lake a Arrow Lake from Intel.
Zen 6 or Zen 6c?
The cores in the 32-core CPU die mentioned in these documents are likely the compact Zen 6c versions, similar to AMD’s 16-core CCD with Zen 4c cores used today. Interestingly, though, the documents don’t use the Zen 6c designation anywhere and only ever talk about Zen 6. Theoretically, this could be because this Embedded series will not use any cores other than compact cores and the specced clock speeds will simply reflect this – thus there will be no reason to make the distinction, even though technically it will be Zen 6c. It is also possible that the compact variant will simply be called Zen 6 and conversely the more powerful version, which is now considered the “vanilla” version, will be given a special name instead (say, Zen 6p as P-Core/”Phat”?).
Will desktop finally get more cores?
Anyway, it is likely that the 32-core dies are compact versions of the core reaching lower clock speeds and not the standard ones. Why? Because otherwise it would be a jump in the number of cores per chiplet from eight to 32, which doesn’t sound likely. That’s why we think Zen 6 could have this compact-core 32-core chiplet for servers and embedded marktet, which would only represnet a doubling compared to the current 16-core Zen 4c-based chiplet.
In parallel, there should be a classic CCD with big Zen 6 cores (and offering the 3D V-Cache options), which will be used in desktop and some server processors. The fact that the compact version is 32-core probably opens up the possibility that the fat version will be 16-core, if the current 2:1 ratio is maintained. So finally, there could be Ryzen processors for mainstream desktop with 32 cores (and also probably 24 cores in a cut-down lower model). As far as we know, Zen 5 won’t bring such an upgrade and will still max out at 16 cores, but in the Zen 6 generation there’s finally a chance that the core and thread count will move higher (for the first time since 2019 and the Zen 2-based Ryzen 9 3950X). However, this is not yet guaranteed and we have no confirmation yet.
Desktop will probably use a different IO chiplet with two channels of DDR5 memory, but since the CPU chiplets will be designed for advanced 2.5D packaging, perhaps silicon bridges with better power efficiency and performance could be used here as well. The question is whether it will still be on the AM5 socket and whether this new more advanced chiplet technology concept will be able to be installed as an upgrade to today’s boards. According to Moore’s Law Is Dead, it’s still possible, especially since DDR5 memory keeps being used – there’s reportedly no indication yet that a new AM6 socket will be used. Again, though, it’s not out of the question at all.
As usual, we must add the caveat that this is an unofficial leak and it is possible that some of the data and information in this source may be an error, misinformation, or some other form of noise. AMD may also still change its plans, so even if the leak is currently legitimate, the prediction may not come true. So for now, don’t take this as a completely definitive thing and count with the uncertainty that is always inherent in this kind of leaked information.
Sources: Moore’s Law Is Dead
English translation and edit by Jozef Dudáš
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