Next-gen version of x86 architecture will probably come with the Panther Cove CPU architecture, which is somehow not the same as Panther Lake
Last year, Intel unveiled plans for improving the x86 platform and instruction set, on which virtually all PC CPUs (from Intel, AMD, China’s Zhaoxin) are based: The APX extension, which breaks through the limitations in the number of registers (somewhat mitigating ARM’s advantage), and AVX10, which is the successor or evolution of AVX-512. For a long time it was unclear when these innovations would ship, but now we finally know.
Intel has not yet publicly announced in which processor generations they actually plan to add APX and AVX10 support. Perhaps because it is not yet certain whether the processors in question will not be affected by some delay or product cancellations. And the company also probably doesn’t want to take the wind out of the sails of previous generations that don’t have these new features yet. But unofficial targets have already leaked out.
According to an employee (or ex-employee) of Intel’s Israeli branch who was apparently involved in the CPU architectures (Stanislav Shwartsman), Intel plans to incorporate these big innovations into a processor architecture called Panther Cove. The Panther Cove core is set to be the next great architectural leap, similar in significance to the recently released Lion Cove. It’s interesting that in this generation, Intel will change the CPUID of the processors after a long time. Intel cores kept reporting “Family 6”, practically since Pentium Pro, and only in Panther Cove will this finally get changed to “Family 19”. This could possibly be to reflect that this core will be a bigger break-away from the past precisely through these new technologies.
Reform plans for the x86 platform
APX involves giving the processor 32 general-purpose architectural (i.e. visible from the programmer’s perspective) registers instead of the current 16. More registers should mean the potential for better performance, and this is one of the things that RISC processors, and currently ARMv8 and ARMv9 in particular, have an advantage in. At the same time, APX should also introduce support for conditional operations and three-operand instruction encoding (which means the result of an instruction does not destructively overwrite one of the inputs as is the case with two-operand format).
x86 processors have actually long used various techniques to mitigate the limitations that these changes address (they internally provide many more registers and use renaming, as well as techniques like store to load forwarding to get around the limite number of architectural registers, and MOV elimination to workaround the disadvantages of two-operand encoding). But even so these changes could bring slightly better performance. But the software will have to be modified or at least recompiled to take advantage of APX. We wrote about this technology in more detail here:
Read more: Intel APX: x86 ISA upgrade to catch up with newer architectures
AVX10 is then the successor to the AVX2 and AVX-512 SIMD instructions, which is supposed to be a kind of solution to the problem of Intel’s own making, caused by the extremely fragmented manner in which the company’s own processors provided 512-bit AVX-512 instruction suport since the introduction in 2017. At first they were provided only by server processors, then with 10nm Ice Lake chips they got to laptops (and in the case of Rocket Lake to desktop too), but then Intel pivoted to using hybrid processor architectures. Unfortunately, the E-Cores in those CPUs can’t do AVX-512, and that spelled the end of its attempts to bring AVX-512 to PCs and laptops (now, ironically, AVX-512 is instead an advantage being offered by AMD CPUs with Zen 4 and Zen 5 cores).
AVX10 proposes to solve this mess with a compromise that adopts the advanced features from the AVX-512 instructions, but effectively reduces the vector width to only 256 bits as in AVX2 (which can be said to still be better than the 128-bit width that ARM is currently stuck with, even with its variable SVE extension, which in theory should have allowed larger widths). AVX10 will also have a 512-bit version that would be functionally equivalent to AVX-512, but only server processors will support the 512-bit mode, while desktop and laptop processors will support just AVX10-256, which E-Cores (albeit likely still using 128-bit units) will be able to provide. Unfortunately, this risks fragmentation, where software and game developers will be unwilling to optimize software for 512-bit processors and will settle for just the “baseline” AVX10-256. We wrote more about how this extension is supposed to work here:
Read more: Instead of AVX-512 comes AVX10. Now also for big.LITTLE processors
Intel has plans for a third innovation or “cleanup” of the x86 platform, an extension or evolution called x86S. This addition is focused more on the system software aspects of the instruction set, operating system startup and similar low-level mechanisms. This update would simplify the architecture by removing some very old legacy features. Its side effect will be that only new 64-bit operating systems will be able to run on the processors after this change – x86S, unlike APX, will actually break compatibility with earlier x86 processors, although not fully. At the level of user-space applications, old 32-bit programs should continue to run, the compatibility breaking should only be at the level of the “kernel” code of the operating systems. If any older Windows or software needs to be run, emulation should be the solution for those needs in the future.
Read more: x86-S: Intel wants to drop legacy compatibility from processors
However, unlike APX and AVX10, there is no word yet that x86S will also be part of the Panther Cove core. So this upgrade or instruction set update may be a distant thing. Intel recently published a new version of the proposals for these changes and it is possible that this is still a matter of ongoing discussion and the final form may yet change.
Unofficial Tick-Tock 2.0: Panther Cove in two years?
According to Shwartsman, Intel is still essentially continuing something akin to the earlier tick-tock model of CPU architecture development, where the big core architecture goes through major upgrades every second generation – those big upgrades were Sunny Cove, Golden Cove, now Lion Cove, and what is supposed to be the Panther Cove core. In between those, the company slots in generations with minor modifications, which was the Willow Cove, Redwood Cove core in the 4nm Meteor Lake processors (which does have some changes compared to Golden Cove and Raptor Cove, they were analyzed in detail by Chips and Cheese if you’re curious).
Between the current Lion Cove, which will be in the Core Ultra 200 processors, and the big Panther Cove upgrade, there is also supposed to be another core representing a smaller update, called Cougar Cove. It is this “intermediate core” that is to be used in the Panther Lake processors, which will be sold as the Core Ultra 300, using Intel’s 1.8nm process node, but these processors will apparently only be productized for laptops. This will make this generation quite similar to the Meteor Lake generation.
Thus, the Panther Cove core will not actually be used in Panther Lake processors (which this naming mind-boggling, but perhaps it could be explained by Intel having to postpone the core architecture by a year, meaning it was originally supposed to be in Panther Lake but plans had to change). But Panther Cove should to appear in the next Core Ultra 400 processors, Nova Lake, which will be the next generation for both desktop and laptop, reportedly using TSMC’s 2nm manufacturing process node. In addition, the Panther Cove core is to be deployed in a version with 512-bit SIMD units (and AMX support) in the Xeon “Diamond Rapids” server processors (where it could possibly be under the Panther Cove-X designation), which should be the next generation of Xeons following the now released Xeon 6 “Granite Rapids” processors. According to some information, the architecture in Xeons might just be directly called “Panther Cove”, while in Nova Lake it might be renamed “Coyotte Cove” (presumably so as not to make the name confusing).
Both Nova Lake and Diamond Rapids should hopefully be products that come out in two years – next fall, the Panther Lake generation without the Panther Cove core will come out as Core Ultra 300, and Nova Lake as Core Ultra 400 should come out sometime in the second half of 2026.
2026 should therefore be the date when APX and AVX10 support could become real for the first time. That is, in Intel’s products. It is not yet clear whether AMD plans to adopt these new extensions to the x86 set and when it would eventually implement them.
Sources: Tom’s Hardware, InstLatX64, Stanislav Shwartsman
Jan Olšan, editor @ Cnews.cz
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