Intel Core i9-12900K megatest: AMD in 2nd place again

Intel Core i9-12900K in detail

The 12th generation Intel Core processors – Alder Lake is now out and we already have the full-fledged tests for you. These processors are significantly different from the previous ones in many aspects and many things are used “for the first time”. Among them are DDR5 memory support, PCI Express 5.0, 7 nm manufacturing process or hybrid concept of small and large cores. It’s time for a detailed analysis!

Intel Core i9-12900K in detail

We’ve kept you up to date on all the Intel Alder Lake processor news as it’s come out throughout the year. But if you happened to miss something, it doesn’t matter. That’s what this first chapter is for, to give everyone a quick overview of what we’ll be covering next.

Alder Lake-S is the first desktop processor to abandon the 14 nm manufacturing process and switch to modern 7 nm technology (before the renaming it was referred to as 10 nm Enhanced SuperFin). This technology is expected to be very much similar to the TSMC’s 7 nm process used to make AMD processors. So after six years (since Intel Skylake processors) there is finally a big change in the manufacturing process.

The design of the processors as such is also significantly changed. These are the first processors ever to use a hybrid concept of small and large cores. So something similar to big.LITTLE from ARM. The most powerful of the Alder Lake processors (i.e. the one we’ll be looking at in these tests), the Core i9-12900K, has eight cores, denoted by the letters “P” (Performance) and “E” (Efficient). The Performance cores have high clock speeds and high performance (19% higher than the Rocket Lake and Tiger Lake processors) and support HyperThreading – two threads per core.

The details of the Golden Cove architecture are discussed in detail in this article. The role of these P cores is to provide performance in games and single-threaded applications. The complementary E cores are then also meant to provide high multi-threaded performance, and are secondarily involved in running low-power processes such as services and background tasks. These cores still have relatively good performance (according to Intel, the IPC is similar to Skylake processors), while needing a significantly smaller die area. In terms of space on a silicon chip, four E cores can fit on a single P core, which is why they’re also referred to as “small” cores, for which we also have an architectural analysis.

The smaller manufacturing process also means a smaller surface area of the entire chip ~209 mm² (this is a reduction of more than 24% compared to Rocket Lake), which is naturally associated with poorer heat dissipation from the surface. The chip is soldered to the heat spreader, but this might not be enough for sufficient cooling. Therefore, to maximize heat transfer to the heat sink, Intel has thinned the chip, narrowed the TIM, and in turn increased the thickness of the heat spreader. The latter was also lengthened a bit, which is not primarily due to better cooling properties, but it doesn’t hurt either. The contact area of the IHS is 38 mm in height, but that should be completely covered by the vast majority of heatsink cold plates.

Also new for these processors is the socket (LGA 1700), where the physical dimensions change after 12 years (from LGA 1156 designed for Lynfield processors). So unfortunately you can’t put Alder Lake processors in LGA 1200 and a new motherboard is needed. It can support either the older DDR4 memory (this usually applies to cheaper boards) or the latest DDR5 memory standard. We have tested with these as well and will continue to test in the future. It’s definitely not as much of a scarecrow as is being spouted around the discussion forums. The timings appear to be high, but the important thing is always the end performance, which across all those applications is very respectable.


With DDR5 memory, you may be surprised that diagnostic tools report a four-channel connection even if you physically have only two modules. This is due to the fact that while with DDR4 memory, a single DIMM has a 64-bit data width and behaves as a single channel, this has changed with DDR5 memory. Each module is internally divided into two channels of 32 bits each. So if you “dual-channel” two DDR5 modules, from the memory controller’s point of view, it’s a four-channel 32-bit connection (instead of two 64-bit channels). But you don’t have to worry about it, functionally it’s more or less the same as the DDR4 channel.

PCI Express 5.0 support is also being introduced with Alder Lake processors. This new bus will be able to be used on ×16 (or ×8) slots for graphics cards.

Warning: Before we get into the tests, it’s important to point out that all tests were run on Windows 10. This is for a number of reasons. Firstly because Windows 11 is still an unrefined environment and any measurements are very quickly out of date, secondly because across installations of different processors on the same OS installation there are reportedly performance distortions (although this may also be due to sloppy cleaning of leftovers from the old platform), and thirdly all processors tested so far have been measured on Windows 10, and with our range of tests it is obviously unrealistic to re-test all processors in the short time we have available. But even if it were possible, the case for W11’s highly variable behaviour is quite strong, and we’ll be sticking with Windows 10 for some time to come, for the sake of accuracy and longevity of results. Sure, on Windows 11 Alder Lake may behave a bit differently because it has a special scheduler (Intel Thread Director) that uses feedback from the CPU. But that is one of the few positives of W11 at the moment, although there is, admittedly, room for discussion.

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    1. We decided to treat is as a 7nm process, since it more or less reflects reality, and Intel more or less wants it to be treated like that. The “Intel 7” does not actually say “nm” anywhere, but the follow up processes will actually be marketed like that. The 20A and 18A processes actually refer to Angstroms, which are non-SI units meaning 0.1nm. So those processes are officially 2nm and 1.8nm when it comes to Intel messaging.

      But when we put that aside, in my opinion it is more useful than not to use “7nm” for the Alder Lake chips. Intel’s 10nm process was in fact roughly comparable to TSMC’s N7 (7nm) process, once Intel got rid of the problems (in the SuperFin or Enhanced SuperFin versions). It is not equal parity in everything, but these technologies can be considered competitive. Calling it 10nm makes it look the process is worse than it is if people assume it is similar to 10nm Samsung or TSMC process node.
      We would basically have to keep reminding people that “Intel’s 10nm is on the level of TSMC’s 7nm”. And it’s not practical to to keep repeating that every time. Ideally this should have been done earlier so that the products were not referred to as 10nm for 2-3 years in press.

      In isolation, the process renaming would not be a good thing, but in a way, Intel only did what TSMC and Samsung did before them. Their processes could be said to be renamed already, so Intel just caught up with that marketing. (Not saying they are at the exact same tech level, but it’s in the ballpark for better or worse).

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