QLC memory has caught on in SSDs, but remains a minority while TLC remains the standard. Increasing capacity by storing more bits in a single cell now appears to have run its course for now, and PLC NAND (5 bits per cell) has yet to materialize. A new approach based on so-called Multi-Site Cell layout may take over. Hynix has now presented this technology in chips that are meant to achieve PLC NAND–level capacity without its drawbacks.
The problem with increasing capacity by encoding more bits into a single cell is that this approach quickly stops “scaling”. This follows directly from how it works—NAND stores data using voltage levels that are preserved (though the retention is not entirely permanent or stable) in a cell. To store more than one bit, a cell must distinguish more voltage levels than just the two states representing 1 and 0. However, the number of required states grows exponentially, while capacity grows less then linearly with added states.
While MLC (2-bit) memory stores two bits using four voltage levels, TLC needs eight levels for three bits and QLC already requires 16 levels for four bits. PLC NAND would need 32 voltage levels for one additional bit (mere +25% extra capacity)—because the voltage values must distinguish all possible combinations of a five-bit binary number (00000, 00001, 00010, and so on).
Current research shows that stable retention of 32 distinct voltage levels in a cell and then reliably reading them back is already too difficult. This would of course also have other negative impacts on performance (the more levels, the longer it takes to program a cell) and endurance (the higher the precision requirements for storing and reading voltage values, the fewer rewrite cycles the NAND can withstand before becoming unreliable). This is why conventional PLC NAND does not currently appear feasible in the near term.
Hynix proposes an alternative way to increase the amount of data that can be stored in a single cell. So-called MSC NAND uses a “Multi-Site” cell, meaning the cell is divided into multiple sections—two in the current design. In a conventional 3D NAND design, the cell has a ring-shaped cross-section, which Hynix leveraged by splitting it using two internal “partitions” in the cell structure. The cell is also slightly compressed into an elliptical shape, so after splitting you end up with something resembling two crescents. MSC NAND then uses these as independent sections for storing voltage levels and thus the written data. This is, of course, not without complications (otherwise NAND would have been designed this way long ago), and it increases structural and manufacturing complexity—for example, both cell sections require their own bitlines to be connected.
The MSC NAND design uses both sections to independently store six voltage levels, which places it somewhere between the data retention difficulty of MLC and TLC NAND. Six levels are not suitable for directly storing an integer number of bits, but the SSD controller or NAND logic processes both six-level values simultaneously by multiplying them (or applying a lookup table), yielding 36 distinct states. These can then be mapped to 32 different five-bit binary values, with four of the possible voltage combinations remaining unused (in the future, these extra states could be used for ECC in theory). The result is that an MSC NAND cell outputs as much data (5 bits) as a PLC NAND cell, albeit at the cost of some additional complexity.
Because writing to individual sections is roughly between MLC and TLC in terms of difficulty, programming performance should be much better than PLC and likely better than QLC NAND as well. Hopefully, this should also apply to endurance (rewrite cycles useful life), the lack of which is the main downside of multi-bit NAND memories. If NAND manufacturers were to switch to this type of cell, more usable storage capacity could be extracted from the area of a single NAND layer. Today’s chips use 3D NAND architecture, and their capacity can also be increased by adding more layers—but that type of scaling too has costs and possibly its own limits. In practice, both capacity-scaling approaches complement each other, making both useful.
Why MSC?
You may be wondering why this approach of splitting cells into two sections is used in the roundabout MSC way, and why the two sections are not simply used as independent cells. If each section had eight voltage levels, it could independently store three bits, you would basically get in TLC NAND chip with double the capacity (compared to a chip with the cell not being split). This is probably because shrinking the cell itself also impacts its reliability. The fact that MSC NAND stores only six voltage levels instead of the possible eight may be due precisely to reduced reliability of the resulting split sections.
The cost of the higher capacity in this MSC NAND implementation may therefore be shorter data retention and reduced endurance (compared to TLC NAND, though it could perhaps still be superior when compared to QLC). It is also possible that, for this reason, the starting cell that is split had to be manufactured larger, which slightly reduces the benefits of this innovation (meaning recording density must first be reduced somewhat before the cell can be split).
It is likely that the combination of six voltage levels per section is a compromise that allowed Hynix engineers to increase capacity and recording density above QLC chips while maintaining reliability at the same or better level. In the more distant past (in 2022), the company also presented a concept in which both sections store data in a “TLC” fashion with eight voltage levels, whose combination yields 64 possible states without redundancy—which would simulate HLC NAND, i.e., a chip with six bits per cell. This apparently has not yet been achievable reliably. MSC NAND with 36 states that is simulating just PLC storage, which Hynix has now presented and reportedly developed in the lab, is likely a compromise and an intermediate step on the path toward that goal.
Ultimately, it is perhaps possible that this technological evolution will turn toward using both cell sections entirely independently in TLC or QLC mode, and instead of the MSC principle we woud effectively end up simply with a changed cell footprint. This will likely depend on what NAND chip structure engineers find optimal in terms of recording density, reliability, and manufacturing complexity (cost). In any case, it shows that NAND memory evolution continues—and once the current availability and pricing crisis passes, we may hopefully return to a situation where SSD capacity per dollar gradually improves over time.
4D NAND 2.0?
Hynix presented this MSC NAND design (in the form of 2 × 6 voltage levels simulating PLC NAND) at the IEEE IEDM 2025 conference in December. In addition to the MSC designation, the company also used the term 4D NAND 2.0 for this future technology (Hynix previously used the 4D NAND label for its 3D NAND design with logic circuits moved to a separate layer using the “Periphery Under Cell” technology). We may therefore ultimately see this designation being used when the time comes to launch MSC NAND as a product.
When chips based on the MSC NAND (4D NAND 2.0) principle will actually appear on the market has not yet been stated anywhere. Translating the concept from laboratory samples into commercial volume production will likely take several years. And it cannot be ruled out that the concept may ultimately prove impractical under mass-production constraints due to excessive complexity or manufacturing defect rates.
Sources: Hynix (1, 2), Blocks and Files, SemiAnalysis
English translation and edit by Jozef Dudáš
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