Kioxia trying HLC NAND with 7 bits per cell, LN2 cooling required

75% increase in capacity at the price of cryogenic cooling

A few years ago, we used to look down on TLC NAND flash that stores 3 bits in a single cell and ask for SSDs with SLC (just 1-bit) flash memory. Since then, TLC has become the norm, and the lower-quality tier was taken over by QLC chips with 4 bits per cell and even worse endurance and performance. And it seems this trend could continue, as Kioxia and WD are preparing “hepta-level cell” NAND that would store 7 bits at once.

Research in this direction is apparently ongoing continuously. Following the development and more or less successful commercial deployment of QLC, work on penta-level cell (PLC) NAND chips was announced by Intel and also by Kioxia.

However, the PLC will only increase the chip capacity by 25% compared to QLC, so Kioxia tried to jump two more bits and store 7 bits in one cell (and one voltage value) as a next step. Such hepta-level cell NAND would increase capacity by 40% compared to PLC and by 75% compared to QLC NAND.

But it will also be a major technological challenge. While adding each additional bit has diminishing returns (in terms of percentage increase in capacity), each such increase requires a doubling of the voltage levels that the cell must be able to set and measure reliably in order to store and then read the data. The number of these resolvable levels therefore grows exponentially. And the technology’s sensitivity, susceptibility to wear and tear, and read error rate also increase accordingly. While MLC requires 4 voltage levels, TLC requires 8 and QLC 16 levels, PLC would be at 32 and HLC chips (with 7 bits per cell) would need to resolve 128 voltage levels. Thus, the differences between these levels will be very small and fluctuations and possible voltage degradation over time will have to somehow fit within this narrow margin.

Distribution of 128 voltage levels in 7-bit Hepta-level cell NAND (zdroj: Kioxia)

But Kioxia says it has already designed and verified in labs a NAND memory concept that would work with such cells and 128 voltage levels. But it’s no simple thing. This NAND uses a new manufacturing process that applies single-crystal silicon instead of poly-silicon crystal, which forms the transistor channel that makes up the memory cells. The single-crystal silicon significantly reduces the noise in the signal (by some 40%), making it possible to better resolve those multiple voltage levels. The channel should also be full, whereas today’s memory uses a hollow channel (“macaroni”).

Classic poly-silicon 3D NAND on the left, single-crystal channel cells on the right (source: Kioxia)

KryoSSD for data center?

This sounds good and the same innovation could hopefully be applied to NAND with loess voltage levels to improve its robustness, endurance and performance. But beyond that, Kioxia is studying another method to make hepta-level cell memories practical: cryogenic cooling. In fact, to reduce noise in the signal even further, this memory is designed to operate at temperatures well below zero.

The study makes a comparison between chips operating at 300 degrees Kelvin (26.85 °C) and 77 K, or -196.15 °C. The combination of this cryogenic temperature and the use of single-crystal silicon is expected to reduce noise levels in the signal by up to two-thirds.

Graph showing how signal noise is lowered using single-crystal silicon and cryogenic cooling (source: Kioxia)

These storage devices would therefore have to be cooled by liquid nitrogen to work. You can probably imagine how complicated that would be. The SSD would have to be outside the computer (server) in a separate unit with a liquid nitrogen cooling system that it would depend on to run. So this solution could realistically only be used in some highly integrated advanced data center. A cooling failure would probably have funny consequences, as it could theoretically even cause data from a large number of units to become unreadable (permanently, even?).

Still, Kioxia says such technology can make economic sense – the company apparently thinks the cost of this complexity could be recouped in higher storage capacity. However, at this point everything is still just in research phase that is demonstrating the possibilities, and it’s a long way from actually being used commercially. We wouldn’t be surprised if cryogenic cooling in data centers doesn’t eventually find any customers and remains confined to labs.

From a sober perspective, it sounds like a better idea to wait until storage capacity is increased by more conventional methods and these technologies can be made to work at room temperatures. In any case, the material research part of the project with single-crystal silicon usage sounds promising and it is possible that we will see it in a more “down-to-earth” version with, for example, PLC or HLC (hexa-level cell, 6 bits per channel) NAND.

Sources: Tom’s Hardware, Kioxia

Jan Olšan, editor for

Flattr this!

Leave a Reply

Your email address will not be published. Required fields are marked *