AMD and Intel announced a surprising rapprochement a year ago, when both companies, together with PC manufacturers and big software players, founded a consortium to oversee the future development of x86 CPUs and their platform. Faced with the growing threat from Arm processors (which was certainly a motivation), this has proved a good choice and will help push modern extensions for the traditional PC processor platform.
The x86 Ecosystem Advisory Group, as the group is called, is now celebrating its first year of activity, and there are already visible results. An agreement has been reached that future SIMD instructions would be harmonized around the 512-bit AVX10 extension, which is essentially AVX-512 with minor changes. Intel discarded previous plans to pivot to a 256-bit variant of the AVX10 set and instead re-embraced 512-bit SIMD width, which means Intel processors will be aligned and cross-vendor compatible with those from AMD. Simultaneously, the company also abandoned plans for the x86S technology, which would have meant a partial break in compatibility—this decision was also made thanks to consultations within this body.
- Tip: Intel cancels x86S, effort to clean up x86 CPUs legacy cruft
- Tip: Intel scraps 256-bit AVX10. P-Cores and E-Cores will get AVX-512
Interrupt handling overhaul
The group is currently celebrating its first anniversary and is announcing further “agreements” between the two competitors on the future direction of x86 processors. The first is a change in the interrupt handling scheme based on a proposal known by the working name FRED (Flexible Return and Event Delivery). Interrupt handling on the x86 platform is one of the areas heavily burdened by the long evolution of this instruction set and the computers based on it—due to keeping backward compatibility since the 1980s.
FRED aims to introduce a new standardized and more modern way of handling interrupts, which should enhance both reliability and performance, and hopefully also simplify operating systems and hardware design. This is an area where discussions have been going on for a long time and multiple alternative proposals have emerged. AMD produced its own more conservative proposal for modernizing interrupts, while FRED from Intel was more ambitious and went deeper. The first version was proposed in spring 2021, and the spec is currently in its ninth revised version. Now, both companies (and presumably also Microsoft and the Linux representatives) have agreed to adopt Intel’s proposal. FRED will become part of future AMD and Intel processors, and operating systems will eventually be able to start utilizing it.
Matrix instructions (AMX in all processors?)
The second news is that the x86 platform is going to adopt standardized instructions for matrix ops (multiplication), primarily used for AI. In principle, these ops are similar to how AI accelerators in GPUs work, but in this case the capability will be tightly integrated directly into the CPU, so these operations will be much easier to use without the need for various cumbersome drivers and “stacks” like CUDA—similar to SIMD extensions.
These new instructions have been named ACE, which somewhat confusingly stands for “Advanced Matrix Extensions for Matrix Multiplication“. The first part of this acronym is reminiscent of the AMX instructions that Intel already implemented for this purpose in Xeon processors (since the Sapphire Rapids generation). The name change, however, implies that some changes have been made and ACE might not be fully compatible with AMX. If there are any differences, Intel may need to add some adjustments to future processor cores to get them to support ACE as well. The important thing is that AMD will also add support for ACE, so software developers will be able to expect compatibility, and hopefully this will bring broader support for these instructions in software.
According to AMD, ACE will no longer be limited to server processors like AMX is. The company writes that support should span devices from laptops to data centers. Which means this technology will most likely arrive in all future x86 CPU cores—both P-Cores and E-Cores in case of Intel.
Big leap for security: X86 receives memory tagging
In the case of AMX, the question of when or whether the extension would get adopted across both Intel and AMD architectures has been on the table for some times. But the last of the new extensions is a bigger surprise. Both companies have agreed to implement an extension labeled ChkTag in their future processors. This is extension introduces memory tagging, a technology that specifies ability to add “tags” to memory content. These tags then help prevent exploits of bugs such as stack overflows, use-after-free errors, and similar—these are among the most commonly exploitable software bugs. It is thus an extension that improves security.
Memory tagging already exists on other CPU platforms like Arm, so x86 is playing catch up with the competition here. ChkTag will add instructions for hardware detection of memory protection violations and strengthen the security of operating systems, virtualization hypervisors, and firmware functions. The specification for this technology will be published sometime during the remainder of this year, but Intel has already shared a little in this blog post.
All three of these technologies are of the type that software can utilize optionally, if developers put in the necessary changes—their benefit will not be automatically applied to all software. Processors will remain fully compatible even with older software that lacks support for these extensions, once they are introduced. Thus, the long-standing continuity of the x86 platform will not be disrupted. Even the memory tagging technology will be implemented in such a way that software that utilises the technology it will run unchanged on older processors without ChkTag support. On old CPUs, the feature will not be used, while on new ones with support, the protection will be active.
This does not exhaust the activities of the x86 Ecosystem Advisory Group; the consortium is expected to continue functioning. AMD and Intel state that they will explore further new instruction set extensions that could be added to x86 processors in the future—provided a clear benefit is demonstrated. The goal remains to ensure that support for various technologies on the x86 platform is stable and predictable, and that software developers can rely on compatibility.
Sources: Intel, AMD, techPowerUp
English translation and edit by Jozef Dudáš
