Intel has had 1.8nm chips since January, while TSMC’s 2nm technology arrived much later. The official names don’t mean much, though—evidence has emerged that Intel’s 1.8nm process has significantly worse characteristics despite the “better number”. Intel has apparently developed versions of their next-gen processor for both technologies internally, but the in-house process suffered worse transistor density and poor performance.
Over the weekend, Moore’s Law is Dead published a video on his channel showing s rough mockup of how the chiplets in Intel’s Nova Lake (Core Ultra 4000) processors will be arranged. More precisely, it covered the Nova Lake-HX variant for laptops, which should be derived from the desktop processors. It also included the die sizes of the chips (or rather, chiplets or tiles as Intel calls them). This report then took a peculiar turn.
Leaker Jaykihn, who has very good information about Intel’s plans, has however expanded on this and provided different, more accurate die size informations for the chiplets. At the same time, however, he said that these die sizes apply only to the chips Intel used for intitial testing, the so-called engineering samples (ES). The final retail chips will have different sizes.
This is strange, because under normal circumstances a given chip is always the same silicon, with production merely fine-tuned over time, or with small changes made to some layers, but the die area cannot change. The reason this will be the case with Nova Lake is rather surprising: Intel first developed Nova Lake processors with its own 1.8nm silicon for the so-called Compute chiplet containing the CPU cores. However, these chips were used only for the first generation of engineering samples that the company handed to its partners for testing. By contrast, the so-called qualification samples (QS) for the final stages of testing and validation, as well as the volume production processors, will exist solely with Compute chiplets manufactured on TSMC’s 2nm process (the N2P technology). This applies to the Compute chiplet variants with 8+16 cores, 4+8 cores, and also the “BLLC” chiplet for gaming processors with a large cache.
The reason is that TSMC’s N2P process (which is effectively a more advanced technology, whereas Intel’s 1.8nm is more directly comparable to TSMC’s older 3nm process) ramped up later, and it turned out that engineering samples would have been available to PC makers too late (only in July or August of this year). Intel would thus have risked losing orders. The company therefore scheduled the development and production of a special version of Nova Lake that uses silicon made on the in-house 1.8nm process instead of TSMC chiplets in advance, as a temporary measure. This made it possible to deliver engineering samples earlier, reportedly sometime in April to May this year. But that is reportedly all; the role of these paralely designed 1.8nm chiplets is to end with that.
Intel’s Own 1.8nm Silicon Had Worse Performance, So It Will Not Go Into Production
The fact that a version of Nova Lake manufactured purely on the 1.8nm process was developed gives Intel the option to bring production in-house if needed—at least for those models where lower clock speeds would be acceptable. According to Jaykihn, however, Intel does not plan to do this. Why not is unclear, but it stands to reason that the design on the Intel 18A-P process has such poor performance (low achieved clock speeds) that it simply would not work in the market.
It is quite possible that Intel invested the no doubt considerable resources needed for launching production of the 1.8nm version of the chiplets in the hope that the results would be better and that some mass production could therefore take place after all (and the money would be recouped). Perhaps those expectations turned out to be too optimistic and the achieved clock speeds too low though, so there was no choice but to limit its use to producing a small number of ES processors for testing.
Intel does apparently still have plans (information about this plan leaked some time ago) to manufacture some Nova Lake processors using the in-house 1.8nm process. However, these will only be lower-end models using a small chiplet with 4 P-Cores and no E-Cores. All higher-performance processors with larger chiplets (4+8 cores, 8+16 cores, and 8+16 cores with large cache for BFC processors) will be sold and mass-produced only with TSMC’s 2nm silicon.
Chiplet Areas in Nova Lake
As we mentioned, all of this surfaced in the context of leaked chiplet sizes for these processors. According to Jaykihn, the 1.8nm Compute chiplet or tile with 8+16 cores (8 P-Cores + 16 E-Cores) used only in ES samples has an area of 111.54 mm². That, however, is the figure for those ES processors. The final version with the TSMC chiplet reportedly has an area of around 97 mm², which points to a considerable advantage in transistor density). Because of the change in size, the package will of course have to change, as will the dummy silicon serving as filler for the space next to the CPU chiplet. The smaller chiplet with 4+8 cores is said to have an area of 52.77 mm² (and this is likely the figure for the final 2nm TSMC silicon). The figure for the BLLC chiplet, that is, the large cache and 8+16 cores, is still missing.
- Read more: First benchmarks of an Intel Nova Lake CPU got out
- Read more: Intel Nova Lake CPUs Without “BFC” Reportedly Weak in Games
Nova Lake-HX for laptops will further have both a SoC or “HUB” chiplet and another PCD (Platform Controller Die) chiplet, which is the equivalent of a chipset, integrated into the processor in Intel’s new laptop processors. The PCD is reportedly 3nm (Intel 3 process) and has an area of 55.92 mm²; this part could probably be absent from the desktop Nova Lake-S processors (and may be replaced by an IOE chiplet expanding connectivity, this remains to be seen).
The HUB chiplet should be present in desktop processors as well as in notebook ones (it is shared by all Nova Lake variants); it is the processor’s uncore with the memory controller, multimedia engines, LP E-Cores, an NPU, and similar components. Its area is 69.41 mm², and it should also use Intel’s 1.8nm process. In this case, however, that will remain so even in the final CPUs. Transistor performance in this part is not so critical that the inferior technology would matter, and TSMC’s 2nm or 3nm process would probably be more expensive to use.
In the package, the HUB chiplet is connected to the Compute chiplet on one side, the PCD on another, and the GPU chiplet on the third. There is another oddity with the last chiplet. First-generation ES samples of Nova Lake processors for desktop and the HX laptop lines contain a GPU tile with four Xe Cores (512 shaders) with the Xe3 (or perhaps Xe3P) architecture, manufactured on the 1.8nm process (Intel 18A-P), with an area of 24.77 mm². Jaykihn states that in the end this GPU variant will only be fitted in Nova Lake-H processors (which otherwise have the same HUB and PCD chiplets and a Compute chiplet with 4+8 cores), however. While the ES samples of the HX and desktop S processors had this larger GPU, their production versions will get a smaller GPU chiplet with just 2 Xe Cores (256 shaders), whose area will be just 15.29 mm².
Incidentally, Intel is also preparing a powerful GPU chiplet with 12 Xe Cores of the Xe3P architecture (1,536 shaders). It will not be used in desktop processors, however—it could reportedly appear in models of the next-generation Razer Lake (Core Ultra 5000). This chiplet is reportedly to be manufactured on TSMC’s N2P 2nm process.
Sources: Jaykihn (1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
English translation and edit by Jozef Dudáš
