N4X: TSMC unveils special processes for high performance chips

TSMC introduces a special X-line of manufacturing processes for high performance chips. Can it beat Intel's high frequencies?

Five to ten years ago, Intel had been the undisputed king of silicon processes, but the delay of 10nm node has ended that and TSMC has been the clear leader since. It is often said that its processes are specialised for mobile use, still remaining inferior to Intel in terms of the maximum achieved clock frequency. But this might change soon. The company will now focus on this very area and high performance chips for PCs.

We have recently reported that TSMC has announced an upgraded N4P process, which is improving the parameters of the 4nm node (which in itself is an improvement of the 5 nm technology). This process should for example have a 6% increase in performance (frequency). Shortly after that, TSMC hass now announced a further variant named N4X, proclaimed to push the performance even higher. Since it is still a derivative of the N5 and N4 processes, this might not seem very notable at first glance, however this process is part of a new TSMC strategy and a new line of its processes, labelled with the aforementioned “X”, that should also keep being applied to future technologies beyond the 4 nm generation.

The Taiwanese company has apparently decided to do something about Intel’s aforementioned lead in max frequency potential (it has to be added that whether this is solely due to the process, or whether it is also due to architecture of Intel’s CPU cores, nevertheless Intel can reach clock rates up to 5,3 GHz, while the competing AMD CPUs based on TSMC technology end at significantly lower peak clocks). Therefore TSMC will introduce its new CPU “X” family, starting with the N4X CPU to the field.

The X processes will be aimed at HPC products, in other word chips centered around peak performance (and therefore frequency). This does not necessarily mean just CPUs for servers and supercomputers, which are commonly associated with the HPC (High Performance Computing) term. This process should help PCs and maybe even GPU to reach higher frequencies as well.

Wafer with 10 nm Intel Xeon Ice Lake-SP CPUs

The N4X process should have the highest performance yet from the entire 5 nm generation. It should be capable of achieving a 15% increase in frequency, compared to chips based on the original 5 nm process (N5). That does not seem like a huge leap compared to the N4P (which itself should achieve +11%, while the N4 has claimed +6%), however the actual gain might be higher. This comparison applies to chips operating with the same 1,2 V voltage. But since the N4X process will simultaneously have more robust transistors and metal layers better suited for voltages above 1,2 V, when compared to the former variants, it will allow the CPUs to increase the voltage a bit further, thereby increasing the achievable frequency even more.

However, an increase in voltage leads to an increase in power consumption, therefore the operation on higher frequencies (after further helping factors implemented on the architectural level of the CPU and its physical design, it might be possible to use up to 1,35–1,5 V, as seen in 7 nm Ryzens) will worsen the energy efficiency and power consumption. Such voltage increases are likely not very suitable for enhancing the overall multithread/throughput performance of a CPU, or GPU performance, but might prove useful for single-thread loads, since it will allow increasing the frequency to higher levels during aggressive turbo boosts. Utilizing this property of the N4X process might hypothetically allow AMD to finally reach frequencies beyond 5 GHz in a reliable manner, similar to Intel, during single-thread turbo boosts. Whether this will come up to an equal level remains a question, decided not only by the process but by the architecture as well.

Performance-optimised transistors, conductors and capacitors: a page out of Intel’s book

TSMC has additionally mentioned some techniques that are used in this high performance 4 nm technology: On the one hand this should include transistors and further structures being optimized in order to manage high currents and as high frequencies as possible. This might likely be done via FinFETs with taller fins, or with a greater number of fins. Such optimizations might also happen on the level of standard libraries (e.g. SRAM cells).

The TSMC N4X process (Source: TSMC)

On the other hand, in order to increase the performance capability, the metal layers will also be optimized. It is not stated how, but it might be achieved through the ability to use more layers, or more robust thickness of the conductors in the upper layers, but it also might be improvements in the conductors’ structure to lower their impedance and the parasitic capacitance.

TSMC further states that the chips will be able to use improved high-density nanocapacitors of the MIM (metal-insulator-metal) type inside the chip. The capacitors should give the chip the ability to manage higher power consumption and current loading, primarily during sudden changes.

The X in N4X apparently stands for Extreme Performance (Source: TSMC)

These improvements in the metal layers and capacitors and even in the FinFETs are strongly reminiscent of what has Intel done with their 10 nm SuperFin process, which has also significantly improved the frequency potential of the until then quite bad 10 nm process (it has literary “repaired” it, because instead of its prior very low clocks it has suddenly reached up to the 5 GHz frequency of the Tiger Lake CPUs). The N4X might therefore turn out to be a very similar modification conceptually, even though conducted on a process that is one generation younger. But since the N5/N4 process likely has not had such significant frequency issues as the original 10 nm Intel process did, the increase in clocks will likely not be as dramatic.

More: Intel 10 nm process back in the game. The SuperFin technology will massively improve clocks.

The conversion from N5 and N4 chips should be easy

TSMC does not say anything about power consumption reductions being achieved (at a given same voltage), whether the effect will be neutral, or whether the performance focused optimization will even  affect the power consumption negatively, when compared with the N4P process. The transistor density has likewise not been commented on at all, so it might possibly be worse than with the N4/N4P process as well, since libraries and structures optimized for performance usually take up more space than the ones optimized for best area and energy efficiency.

What will remain is the partial compatibility with the design rules of the 5 nm process. So the physical design of the chip will not have to start completely from the ground, the engineers will be able to reuse work done on previous designs, when porting them to N4X from a different TSMC 5 nm and 4 nm process variant.

Availability in 2023/2024

So far we do not know which CPUs or GPUs might be produced using this new high performance process. A possible client is AMD and its Ryzen CPUs, but competing ARM CPUs are also a possibility. N4X definitely might be attractive for IBM and its Power and Z CPUs – should the company wage another transition shortly after being forced to move to Samsung. It is however in question, whether such CPUs will not prefer the higher energy efficiency possible with 3 nm process, which might become available at the same time, in parallel with this performance oriented technology. The currently leaked roadmaps have not shown any 4 nm products coming from AMD, in terms of CPUs, it was reported it might jump from 5 nm (Ryzen 7000) directly to 3 nm (Ryzen 8000).

Cleanroom of TSMC semiconductor fab

Acording to TSMC, the N4X process will enter the so-called risk production in the first half of 2023, which means it is still some years away, even though the first 4nm mobile SoC (made on the first generation of the N4 process) are already starting to appear (MediaTek Dimensity 9000). Risk Production means an initial trial operation, followed by regular commercial volume production usually after some time. CPUs based on the N4X process might therefore realistically appear on the market at the end of 2023 or at the start of 2024. Note that 3nm chips based on the N3 process are slated for debuting in the first half of 2023. Ideally we would like future prospective X processes based on 3 nm and 2 nm to appear sooner after the first CPU generation of these process nodes. It is possible that TSMC will strive for this in the future. In any case these X technologies might be an interesting addition to the portfolio of the leading edge silicon process tech and might allow for some very interesting hardware to be made.

Source: TSMC

English translation and edit by Karol Démuth, original text by Jan Olšan, editor for Cnews.cz


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