Presenting at SIGGRAPH 2026, Nvidia has revealed more details about its latest upcoming GPU generation—Rubin. We are talking about the Rubin GPU for data centers and artificial intelligence though, not gaming graphics cards. The Rubin AI accelerator will be more important to Nvidia, though, as it promises the company hundreds of billions of dollars more in revenue from various firms hoping to establish themselves in the AI sector.
The Rubin GPU consists of two interconnected dies, each of which will have a typical size at the very limit of what can be manufactured (around 800 mm²). The complete GPU is expected to contain 336 billion transistors. The dies are interconnected via the NV-HBI interface, although they are apparently also capable of operating independently. Nvidia had previously planned a four-die package as well, but according to behind-the-scenes reports, this version was canceled due to technical issues.
Nvidia promises that the Rubin GPU will deliver up to 25 PFLOPS of performance when using low-precision four-bit floating-point values (NVFP4). With sparsity, performance should be equivalent to 50 PFLOPS, a figure intended for inference workloads. Nvidia claims in its materials that this represents up to five times the performance of the Blackwell generation, but that is a bit odd. Nvidia has listed Blackwell’s AI performance at 20 PFLOPS (also including sparsity), which would make Rubin only 2.5× faster. It appears that Nvidia is comparing the dual-die Rubin GPU with a single-die Blackwell GPU, even though the Blackwell generation already included an equivalent dual-die version, which Nvidia presented as its flagship model when it was unveiled—just as it is doing now.
For neural-network training, performance of 35 PFLOPS can be expected (also using NVFP4). Nvidia does not disclose power consumption, but the TDP is likely to be very high, exceeding 1000 W.
Nvidia states that the GPU delivers 130 TFLOPS of baseline compute performance in FP32 precision using general-purpose shaders and 400 TFLOPS in matrix-based AI calculations using Tensor Cores. For scientific computing using FP64 precision, the GPU provides 33 TFLOPS of compute performance. Nvidia has made little progress in this type of performance in recent years, and Rubin is actually slower than the four-year-old Hopper generation. Nvidia says that software emulation using Tensor Cores can deliver up to 200 TFLOPS. However, this is not a fully equivalent replacement for standard FP64 compute capability.
Nvidia states that the complete GPU consists of 896 Tensor Cores, which use the third-generation Transformer Engine architecture. The number of conventional SM blocks has not been disclosed, although there could be 224 of them, as Nvidia has traditionally used four Tensor Cores per SM block. The number of conventional general-purpose compute units is not stated directly. Based on a schematic image of the die—or rather, the two dies forming the GPU—it appears that each die physically contains 124 SM blocks organized into quadrants (two containing 30 blocks each and two containing 32 blocks each). This means that the complete dual-die GPU actually contains 992 Tensor Cores, but Nvidia expects some SM blocks to always be disabled to improve yields. Dies with certain defects will therefore still be usable for the the highest-end commercially shipping configuration, just like defect-free dies.
Each die has its own HBM4 memory controllers with a total bus width of 4096 bits, as well as two separate L2 cache blocks. The memory attached to one die will have a capacity of 144 GB and bandwidth of 11 TB/s, which results in 288 GB of memory with total bandwidth of 22 TB/s when both halves of the GPU are combined.
Two compute dies, two I/O chiplets
It is not entirely clear whether the GPU consists of two identical dies. Nvidia’s diagram suggests that the “left” and “right” halves are different. While the number of compute units is apparently the same in both, their connectivity should differ. According to Nvidia, one half includes a PCI Express 6.0 ×16 interface for the primary connection to the system and NVLink v6 connectivity for connecting to networking switches—which Nvidia develops specifically for this purpose—and to other GPUs in the rack. The combined bandwidth of these interfaces is said to reach up to 3600 GB/s (presumably meaning 1800 GB/s in each direction).
According to Nvidia, the second half does not include a PCI Express interface, but only NVLink C2C interfaces used to connect to the system processor (such as Nvidia Vera). These interfaces are expected to provide combined bandwidth of 1800 GB/s (again, possibly the sum of 900 GB/s in each direction). Nvidia could use two identical dies featuring the same I/O interface block, configured differently after manufacturing in theory . However, given its revenue, Nvidia can certainly afford the costs of duplicated tape-out and mask production, so Rubin may indeed use two different silicon variants.
However, based on photographs of the samples—or mock-ups?—presented by Nvidia, the NVLink and PCI Express 6.0 interface blocks appear to be implemented as separate I/O chiplets, probably manufactured using an older process node. This likely explains their differing feature sets. If so, both compute dies are probably identical and only one tape-out was required for them (excluding the separate tape-outs for the I/O chiplets), while the I/O chiplets differ—including in size.
It is possible that the NVLink v6 interface with its higher lane count was also intended to connect two additional Rubin dies in the canceled four-die version. If not, perhaps only two dies within the four-die package were intended to be interconnected at a time, meaning the complete package would have behaved as a pair of separate GPUs. However, this is only speculation. We may never learn what the original plan was if it’s true that the four-die version has been canceled.
Availability this year
Nvidia will apparently sell the GPU as a standalone product as well, but the company will likely focus on complete servers and racks (which is one of the factors behind its extremely high revenue). One NVL72 rack is expected to contain 72 Rubin GPUs (which presumably means 144 dies), 36 Vera processors, and 36 NVLink switches. According to the company, Rubin GPUs should begin shipping sometime in the second half of this year, although no exact date was provided.
Sources: techPowerUp, Nvidia (1, 2)
English translation and edit by Jozef Dudáš
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