It’s roughly two weeks until AMD releases processors with the new Zen 5 architecture. This week, we finally got proper details on these CPUs’ architecture, which AMD revealed at the Tech Day event. So, we can now break down the changes the company has made to the core, compared to Zen 4 – and they’re pretty extensive, probably more so than they seemed in June. And AMD also reiterated its promise of a 16% increase in IPC for these CPUs.
More ALUs, stronger backend, unified ALU scheduler
As previously leaked, Zen 5 adds ALUs for the first time since the first Zen 4; there are now six ALUs instead of just four. Intel’s new core, Lion Cove, has the same number, but ARM or Apple are already at 9-10 (however, note the law of diminishing returns applies with increasing numbers of units). So the Zen 5 core can handle up to six common arithmetic logic instructions in a single cycle.
However, for some operations, the increase in resources may be even greater. In fact, in previous cores, three of the four ALUs were simple, so they could not do more complex operations like multiplication, which only one “complex” ALU could do. The two newly added ALUs in Zen 5 are apparently both complex units, as this new core can perform three integer multiplications per clock, a three-fold improvement. AMD has also increased the number of branch units, these are three instead of two (present presumably on the same ports as the simple ALUs). Thus, up to three jumps, or branches, per cycle can be processed.
AMD has increased the number of registers in the physical register file used for general purpose registers (for ALU operations) to 240, a slight increase from 224 in Zen 4. There is a far larger increase in the physical register file for SIMD (FPU) registers, where Zen 4 had only 192 registers, but Zen 5 has 384 registers. These physical registers are used to rename architectural registers (which are exposed to running programs) during the out-of-order and parallel instruction processing, and more registers give the core broader optimizing options.
AMD also made changes to the schedulers from which instructions are fed to the units. Whereas Zen 3 and 4 used four separate schedulers of 24 entries each – one for each ALU (and the AGUs or branching units associated with those ALUs), Zen 5 instead has a 88-entry deep unified scheduler for all six ALUs (and branching units) and a second 56-entry deep unified scheduler serving all AGUs (Zen 2 previously had a unified scheduler for AGUs). This is intended to allow more flexible allocation of instructions to ALUs, which Mike Clark says has become more important with the increased number of ALUs than in previous cores with only four ALUs. The new scheduler would be more efficient even with the same number of entries according to AMD.
There are four AGUs and thus four load/store pipelines compared to three in Zen 4. The core can perform up to four memory or L1 data cache reads (loads) to registers per cycle. Only two writes (stores) can be performed per cycle, and a maximum of four memory ops formed from a combination of writes and reads can be performed each cycle.
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