Not long ago, rumors surfaced that AMD’s upcoming Zen 6 CPU architecture would be based on 3nm node, but on a 2nm process. At the time, it was unclear whether those YouTube reports were credible. But time has validated them – AMD itself has now confirmed that its next-gen CPUs will use the 2nm node, and even revealed that its 2nm processor has already completed tape-out at TSMC, as one of the very first chips to do so.
In an unusual move, AMD issued a press release announcing that the company achieved a particular milestone in the early stages of preparing its future server processors, codenamed Venice, for manufacturing. The company is touting this achievement because Venice is a chip (specifically, a compute chiplet with CPU cores, we are talking the processor’s CCD here) that uses TSMC’s latest 2nm process. It is reportedly the first “high-performance computing (HPC) product” successfully prepared for manufacturing on this technology. This refers to the completion of the tape-out phase and what AMD calls the “bring-up,” which likely means manufacturing the first wafers and samples – not yet full commercial manufacturing.
AMD says this milestone demonstrates its strength in advanced chip design. The announcement also vaguely references a form of “co-optimization” of the architecture and manufacturing process in collaboration with TSMC. This implies that AMD has become a key customer with influence over the manufacturing process, with TSMC possibly even shaping it to fit its needs, or considering them during the development phase. This kind of influence was previously attributed mainly to Apple and, likely, to Nvidia as well (though other players may also enjoy similar privileges).
However, this announcement doesn’t necessarily mean that AMD is leading the 2nm chip race overall. Apple is typically first, followed by other mobile SoC manufacturers (Qualcomm, MediaTek, formerly Huawei/HiSilicon). Apple is likely still first with 2nm process adoption – that is likely that is precisely the reason why the press release avoids claiming the “first 2nm product” and instead highlights the “first 2nm HPC product.” HPC (High Performance Computing) typically refers to products for supercomputers, servers, high-endworkstations, and intensive compute workloads, so this allows AMD to set aside mobile SoCs for phones and laptops from Apple.
Two Implications for Zen 6
Twenty years ago, “Venice” was the codename for the first 90nm processors from AMD’s Athlon 64 family. The name has now been reused for the Epyc 9006 series – the next generation expected to feature Zen 6 cores. This is thus a clear confirmation that Zen 6 processors will be produced on TSMC’s 2nm node. However, no specific variant was mentioned, so we don’t yet know whether claims from the YouTube channel Moore’s Law is Dead – that AMD will use a high-performance variant of the node, N2X – are accurate. Until now, AMD has presumably relied on standard versions of TSMC’s process nodes.
This news also confirms another major detail: Zen 6-based processors will arrive next year, at least for servers. For the first time, AMD has officially stated that Epyc 9006 “Venice” is set to launch in 2026 (or that everything is currently on track for a 2026 release – though delays cannot be ruled out). Typically, it takes roughly a year from tape-out to commercial launch, so there’s ample time for “Venice” to hit the market in the second half of next year.
Will There Be More 2nm Chips Beyond “Venice”?
It’s worth noting that the 2nm node might be reserved only for server processors, there’s the possibility that desktop/consumer versions (i.e., Ryzen CPUs, which are of greater interest to most users) will not use the same process. AMD could opt to save costs by manufacturing them on an older node, in theory. And even within the server lineup, the 2nm process might apply to only select models. For instance, the server variant of Zen 5 with “dense” Zen 5c cores is already built on the 3nm node, whereas all other Zen 5 chips are on 4nm.
Still, there’s a good chance that other Zen 6 variants will also use the 2nm process. Developing an architecture often involves tuning it for a specific silicon technology, and using a single process node for all die designs simplifies this effort. Targetting multiple nodes increase the complexity of validation and testing, whereas a single process node target saves engineering resources.
Such openness about a future product milestones isn’t all that common. It raises the question of whether AMD might be feeling pressure due to the fact that Zen 5 wasn’t received as warmly last year as the company may have anticipated (and whether the original performance targets for it might have been slightly more ambitious than what was realised).
Alternatively, AMD could be engaging in positive PR ahead of its upcoming earnings report, expected in about two weeks – perhaps bracing for results that may be disappointing for the market. It might also be a move to boost investor sentiment amid market turmoil driven by U.S. political developments, which have hit AMD stock particularly hard.
Epyc Production in the U.S.
Speaking of the U.S., AMD also announced that it has launched production of the AMD Epyc 9005 server processors (the current generation based on Zen 5) at TSMC’s Arizona facility (Fab 21) and confirmed (validated) full product compatibility. This allows AMD’s server processors for the U.S. market to be manufactured locally – whether due to the threat of import tariffs or national security requirements. According to analysts, manufacturing in Arizona is slightly more expensive, so the rest of the world will likely continue to receive Epyc chips produced in TSMC’s Taiwanese fabs.
Source: AMD
English translation and edit by Jozef Dudáš
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