The majority of PCs, mobile and server processors have consolidated around the x86 and Arm architectures, with RISC-V having some potential—currently it’s limited to embedded. However, China is home to one of the few exceptions: Loongson processors (the only other might be IBM Power). The company has now introduced a new generation of server CPUs, which is the most powerful branch of this CPU lineage yet, offering up to 64 cores.
In 2023, Loongson developed a new generation of processors labelled LS3A6000, or 3A6000 for short, which introduced a new LA664 architecture with significantly improved performance per MHz (commonly referred to as “IPC”). Following these client CPUs, the company announced a much more powerful server variant last year: the LS3C6000 (or 3C6000), which is now finalized and heading to market.
It’s in the (Linux-based) server ecosystem where Loongson could find a stronger foothold in China, unlike the PC and laptop sector, where a CPU with a completely own instruction is bound to struggles to gain traction. These CPUs are the only ones in the world based on the LoongArch architecture (which has evolved from MIPS, though).
Loongson LS3C6000
The Loongson LS3C6000 uses the same LA664 architecture but offers significantly more cores. These processors are chiplet-based and can be composed of one, two, or four dies, forming configurations with 16 to 64 cores. Their interconnect design appears similar to the first-generation AMD Epyc (7001 “Naples”) and Threadripper processors, where each chiplet had its own memory controller and PCI Express interface—effectively operating as a 2S or 4S system within a single package.
Loongson LS3C6000 employs a custom coherent interconnect logic called Loongson Coherent Link to connect the chiplets. Unlike AMD’s Infinity Fabric, it doesn’t appear to use PCI Express as the physical layer (the PCIe controller/PHY count doesn’t match with that). Each chiplet seems to feature dedicated logic and PHY purely for Loongson Coherent Link connectivity—this block is marked in released dieshot. Loongson previously used the HyperTransport standard derived from old AMD Opteron server CPUs, and Loongson Coherent Link could be its successor.
Each chiplet includes 16 LA664 cores with 32MB of shared L3 cache (only shared within the chiplet; access to cached data across chiplets has to go via the interconnect). The LA664 cores use a 6-issue out-of-order architecture with 4 ALUs, 4 AGUs, and 4 SIMD/FPU units, along with 64KB of L1 instruction cache, 64KB of L1 data cache, and 256KB of L2 cache. SMT is supported, allowing each core to handle two threads simultaneously, boosting multithreaded performance. The LoongArch instruction set also includes its own set of 256-bit SIMD instructions—basically an alternative to the AVX2 in x86 processors.
Like x86 CPUs, these processors have a separate security subsystem called Loongson SE, featuring a dedicated simple LA264 core. It supports Chinese cryptographic standards SM2, SM3, and SM4. Besides PCIe connectivity, the LS3C6000 processors also offer SPI, UART, and GPIO interfaces for additional devices and peripherals.
Single-chiplet configurations (LS3C6000/S) have a typical power consumption of 100 to 120 W and feature 16 cores / 32 threads at 2.2 GHz. This setup includes a quad-channel DDR4-3200 memory controller (each chiplet actually physically supports four channels), including ECC support—making even this relatively small configuration capable of handling quite large RAM capacities. The CPU offers 64 PCI Express lanes. However, the generation is unspecified—if it were PCIe 4.0 or even 5.0, the company would likely highlight that, so it might still be the old and slow PCIe 3.0 standard with just 1 GB/s per lane.
Dual-chiplet models (LS3C6000/D) have 32 cores and 64 threads at 2.1 GHz, with 2×32MB of L3 cache and typical power consumption of 180–200 W. Quad-chiplet models (LS3C6000/Q) offer 64 cores and 128 threads at 2.0 GHz with 4×32MB of L3 cache and typical power usage of 250 to 300 W.
The dual- and quad-chiplet configurations share the same I/O capabilities: 128 PCI Express lanes and an eight-channel DDR4-3200 memory controller. Thus, the quad-chiplet models don’t utilize the potential for 16-channel memory configurations.
It appears that Loongson currently does not offer SKUs using chiplets with partially disabled cores, nor multiple tiered models with different clock speeds. Given the relatively low production volume, it may not be economically interesting to do binning of individual chips. However, the CPUs support dynamic clock speed and voltage scaling, as well as clock gating, allowing inactive cores (at the module/chiplet level) to be disconnected from the clock signal. There’s no mention of power gating (complete power shutoff to parts of chip), so energy savings won’t match those of more advanced CPUs with that capability.
Performance competes with older Intel CPUs
According to Loongson, these processors are competitive with Intel’s older 10nm Ice Lake-SP server CPUs from 2021 (though it’s worth noting those were already behind AMD’s 64-core Epyc 7002 from 2019). The highest-performing 64-core configuration is compared to the Xeon Platinum 8380 (the top Ice Lake-SP model with 40 cores and 80 threads). They’re not aiming to rival today’s best server processors, but rather to offer a lower-cost alternative.
For China, the key point may be that this is a domestically developed solution. It’s not entirely clear where the chips are manufactured, but it would make sense if they’re being produced on silicon processes provided by Chinese foundry SMIC—making the entire chip supply chain independent of foreign vendors like TSMC or Samsung.
Loongson has now officially announced these processors, though it’s unclear whether they’re immediately available on the market. For smaller players like this, it can often take substantial time before a product becomes truly purchasable. In any case, the CPUs will likely only be available in China, with exports being unlikely.
Sources: HardwareLuxx, Loongson
English translation and edit by Jozef Dudáš
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