We wrote that AMD has once again canceled its plans to produce Arm processors. However, the industry veteran IBM is now moving in the opposite direction, actually adopting the Arm instruction set. But it is doing so in an interesting way—it is not replacing its existing architecture (or at least not yet), but is introducing a processor that features its own instruction set while also being fully compatible with the Arm architecture.
IBM has now introduced a new generation of processors for its Z Series mainframes (or z Series—the graphical representation has changed over the years) that simultaneously support two modes—its own original instruction set and the 64-bit Arm instruction set. The latter will be used to run server applications on Linux (IBM calls this platform LinuxONE). From a software perspective, the processor will therefore offer direct compatibility with software released and optimized for this platform without requiring any modifications. In addition to their specialized or legacy software stacks and systems intended for mainframes, mainframe users will thus be able to flexibly run mainstream server software on the same hardware.
It should be noted that this news does not concern the IBM Power processors, which you are probably familiar with (IBM has recently released the new Power11 generation in this line). Completely separate from PowerPC and Power processors, IBM has been maintaining the developing another platform all this time, the so-called mainframe computers—large-scale systems for highly demanding mission-critical applications and systems, with a claimed 99.999999% availability.
This platform called IBM Z Series, Z Architecture, or z/Architecture is a continuation of the historic IBM System/360 (from 1964), System/370 (1970), and System/390 (1990) mainframes and still supports running software from those eras—with a 64-bit instruction set in addition to support for older instruction sets. The first generation of the 64-bit Z architecture was released in 2000, and, if we are counting correctly, ten generations have been produced since then, with the latest designated z17 (the numbering began with z9) and featuring a processor also designated IBM Telum II.
New Dual-ISA Z Processor
We do not yet know what the newly presented processor with dual support for the Z and Arm (“LinuxONE”) architectures will be called. It may be Telum III and should presumably power the z18 generation of computers. Despite the dual-ISA support, the CPU will meet the requirements of the mainframe class in terms of reliability and other features specific to this segment. The chip is manufactured using a 2nm process and contains 11 cores—or apparently there’s 12 physical cores in silicon, with one always disabled. This allows chips with defects to be used. The cores are planned to clock at 5.7 GHz or higher (“5.7 GHz+”) and they support SMT, with each processing two threads. The processors should be grouped into nodes of eight units (so-called drawers) in the Z systems.
All of these cores support both the IBM Z instruction set and the 64-bit Arm instruction set, specifically Armv9.3 version including SVE and SVE2. In total, this amounts to 2792 Arm instructions (modern ARM is not particularly “RISC”), and the core has 239 physical registers for them. This is full native support for binary code running on the core (including compatibility with the SystemReady standard), rather than some form of emulation or merely features designed to accelerate emulation. This instruction set uses the little-endian data format (byte order), whereas the Z architecture is natively big-endian.
At the Hot Chips conference, IBM presented some details confirming that the cores natively support both instruction sets throughout their entire pipeline. To achieve this, IBM added the necessary capabilities to the cores or redesigned various units so that they could operate in both modes when it was not possible to straightforwardly reuse the unit designed for Z instructions. For example, branch predictors or the TLB could be adapted without major changes, while execution units required smaller or larger modifications—for example, supporting SVE/SVE2 SIMD instructions required redesigning the control logic, and the execution units required adding support for working with FP16/Bfloat16 data types.
The processor makes various specialized Z architecture accelerators available to software running in Arm mode as well, such as cryptography acceleration, gzip compression, or AI acceleration units. While these are used through CISC instructions in the Z architecture, in Arm mode with Linux they are exposed as separate devices.
The Linux OS is expected to run on these servers within KVM virtualization, which allows both Linux in Arm mode and Linux running on the s390x instruction set (and in big-endian mode) to run simultaneously. In addition, the original and default operating system of the z/OS platform can also run on the cores—logical core partitions can be dedicated to each of them on the processor. According to IBM, the instruction-set mode processed by a core (or thread) can be switched within a few nanoseconds.
Each core has a very large private L2 cache with a capacity of 36 MB. Although this is a private cache of each core, the combined L2 caches of all the cores are made available as a virtual L3 cache (IBM lists its capacity as 432 MB, which would correspond to all 12 physically present cores, so perhaps cache blocks from the disabled core are also made available?). The processor also has a virtual L4 cache with a capacity of 3.5 GB. This should presumably be a combination of all L2 caches in the eight-processor node (“drawer”) that forms a building block of Z Series computers. This rather unusual architectural trait is inherited from the previous IBM Telum (z16) and IBM Telum II (z17) processors.
Like previous IBM mainframes, this hardware will probably not see widespread use and will keep being used in the in the same areas where Z systems are being used now. Whether IBM will manage to reach new markets or achieve broader adoption by supporting Arm Linux on the Z architecture remains to be seen. Supporting two historically unrelated instruction sets on the same processor is certainly an interesting achievement, although it is true that it is not entirely unprecedented—the 32-bit and 64-bit Arm instruction sets are not compatible, so CPU cores that supported both were, in a certain sense, a similar concept. But probably not as complex to implement.
In the past, proposals were made for processors supporting both the Arm and x86 instruction sets simultaneously to provide compatibility with existing software, usually presumably with the intention of gradually transitioning to Arm and eventually abandoning x86. But such CPUs would naturally have to be developed by AMD or Intel, which own (and jealously “guard”) the license to the x86 instruction set, and doing this would not be smart tactic for these companies. The world’s transition from x86 processors to the Arm architecture would take away their unique competitive advantage. IBM is now demonstrating a similar architecture and showing that it is technically possible to build such a dual-ISA processor—although the silicon is more complicated and likely more expensive to manufacture because of the additional logic is required in each core. Whether anyone else will follow this concept remains an open question.
Sources: IBM, ServeTheHome
English translation and edit by Jozef Dudáš
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