Chiplet GPUs from AMD confirmed in Linux code
After Ryzen and Threadripper chiplet CPUs, AMD’s GPUs are apparently next to take this approach using several smaller chips to replace a single bigger one. AMD staff have now confirmed that the next generation of compute GPUs, likely coming next year (possibly as the first 5nm GPUs), will consist of at least two chiplets. Chiplets have not yet been confirmed in gaming graphics cards, but they could appear in the new RDNA 3 architecture.
In the world of processors, we have had “chiplets” for a while, which means that instead of one chip, a processor is made up of several smaller components, particularly heterogeneous ones, as is the case with 7nm AMD processors. In recent years, there have been indications that this innovation could be carried over to GPUs, but with the exception of the extremely complex Intel Ponte Vecchio accelerator for the Aurora supercomputer, which generally defies most chipmaking norms, nothing has been confirmed yet.
Until now. The first chiplet GPU has now been confirmed in AMD upcoming portfolio, after this was admitted by employees in patches sent to Linux driver code. They add support for GPUs codenamed Aldebaran, and the power management patch states that the GPU will be composed of multiple pieces of silicon, where the “primary” one supports the reading of telemetry consumption data, while the “secondary” does not and also cannot set consumption limits, which must be done via the primary silicon. Other parts of the code then refer to “die0” and “die1”.
However, Aldebaran is not a GPU meant for Radeon gaming cards. It should be the successor to last year’s Arcturus GPU (Instinct MI100), a compute GPU for the AMD Instinct series of cards used in scientific computing and artificial intelligence applications. Aldebaran apparently uses CDNA 2 architecture, a new generation following CDNA in the Arcturus chip. It could likely be released next year.
Reportedly 2 × 8192 shaders, 8192-bit HBM2E
The Linux code does not reveal the specifications of this GPU, but according to the leaker nicknamed Kepler_L2, this GPU should have two chiplets, each with 128 CUs (8 shader engines of 16 CUs each), which should mean each has 8192 shaders. However, the resulting product may reportedly have a portion of the CUs always turned off, so as a result, the accelerators based on it that AMD will actually be shipping may not have as many units.
The full config of Aldebaran is 2 dies x 8 Shader Engines x 16 Compute Units, but MI200 might be only 224 CUs enabled ? https://t.co/RO7RptgYSk
— Kepler (@Kepler_L2) June 10, 2021
It should be a relatively basic MCM design, where it is said that only two compute chiplets will be used, without some IO chiplet that would integrate them together. Aldebaran would thus resemble the simpler first generation of Epyc and Threadripper.
I believe it's a simple MCM design like Naples.
— Kepler (@Kepler_L2) June 10, 2021
HBM2E chips are to serve as memory. According to Patrick Schur, there’s eight packages. This would mean a 8192-bit bus, theoretically providing up to 2.4–3.0 TB/s bandwidth, roughly. But it’s probably because each chiplet has its own four HBM2E packages (4096-bit bus width).
MI200 has eight HBM stacks in total.
— Patrick Schur (@patrickschur_) June 10, 2021
VideoCardz notes that the Vega 20 computing chip (Radeon Instinct MI60) was the first AMD product to be built using a 7nm process two and a half years ago, with the Vega 20 being the predecessor of the Arcturus GPU in the very same product line. If history were to repeat, Aldebaran might be the first 5nm chip (or 5nm chiplet product) released by AMD.
There have also been rumors that even the future Radeon GPU, called Navi 31, could have a chiplet design. The same source claims that it should have two compute chiplets, perhaps each with 5120 RDNA 3 shaders. In this case however, the construction may already be heterogeneous, with added IO or control chiplet binding them together. Kepler_L2 states that the lower GPU model, Navi 33, will have one compute chiplet (while Navi 31 will consist of the same chiplets, but two), but this does not mean that Navi 33 will be monolithic. This would imply that in addition to the compute chiplet, it has another piece of silicon, perhaps an IO chiplet like used in Ryzen (although with a GPU, the memory controller could likely be located in the compute chiplets).
These GPUs with the RDNA 3 architecture could hopefully also be released by the end of the next year – Q4 2022. We’ll see if the compute-focused Aldebaran comes out sooner. But the GPU sector is obviously in for some fresh air. Whether AMD will benefit from this is difficult to say so far, because not every innovation ends up in a success and, as has already been said, this should be the first time a chiplet solution has emerged in GPUs. Memory bandwidth and scaling requirements could cause the chiplet approach to not work as well as it does in CPUs now.
Sources: VideoCardz, Kepler_L2/Twitter (1, 2, 3, 4), Patrick Schur
Translated, original text by:
Jan Olšan, editor for Cnews.cz
