Gaming used to be a strength of Intel CPUs, but that changed with AMD’s “X3D” chips featuring 3D V-Cache. First the Ryzen 7 7800X3D, and then last year’s Ryzen 7 9800X3D, has gained significant lead in games , while Intel’s new Core Ultra 200 lineup has disappointed. But next year, Intel may have a shot at reclaiming ground—it’s preparing its own version of CPUs with large L3 cache, which could bring similar benefits to 3D V-Cache.
Details on these processors have now surfaced online from the leaker known as OneRaichu. As always with such leaks, take them with a grain of salt—mistakes or misinformation are possible. Still, the info is intriguing.
BLCC
According to OneRaichu, Intel’s alternative to 3D V-Cache, referred to as BLLC (Big Last-Level Cache), will be featured in two Nova Lake desktop processor models. Both will be based on a Nova Lake variant with a single CPU chiplet—one higher-end model with 8 P-Cores and 16 E-Cores, and a lower-end version with 8 P-Cores and 12 E-Cores. Essentially, they’ll be the counterparts of today’s Core Ultra 9 / Core i9 and Core Ultra 7 / Core i7. Nova Lake processors will also include 4 LP E-Cores in the SoC chiplet in addition, but those likely won’t play a significant role in gaming.
Earlier reports suggest that the BLLC (also written as bLLC in some references) cache could offer a capacity of 144 MB. It’s still unclear whether this is the total L3 cache of the CPU or if the 144 MB will be added to the L3 cache already present in the CPU (for example, the current Core Ultra 9 285K already has 36 MB in total). The TDP for BLLC CPUs is reportedly 125 W. As usual, the maximum turbo power will be higher.
It appears that BLLC won’t be available in CPUs with multiple compute chiplets. Leaks suggest Nova Lake will also come in dual-chiplet versions, supporting up to 52 cores (16 P-Cores, 32 E-Cores, and 4 LP E-Cores in the SoC chiplet). However, these will not be available as BLLC gaming variants.
That might be due to the way Intel has implemented BLLC. Based on leaks so far, it’s not a separate SRAM chiplet connected via 3D stacking on top of or beneath the CPU chiplet. Instead, it might use “2.5D” packaging, where the cache chiplet is placed alongside the CPU chiplet and connected via a silicon bridge or interposer. Alternatively, BLLC could be integrated directly into the CPU chiplet itself—significantly increasing its size. That would require a separate mask and tape-out.
A monolithic large chiplet could deliver excellent performance and potentially avoid the limitations on clock speeds due to voltage sensitivity, a known drawback of AMD’s X3D processors. With 2.5D packaging, such voltage or clock speed limits could also happen in theory but are not guaranteed to. Either way, both designs take up more space, and that may be the reason why BLLC can’t be combined with dual-chiplet CPUs.
Will BLLC be as good as “X3D”?
Just having a large cache doesn’t guarantee great results, so it’s still unclear whether Intel will be able to match the gaming performance of AMD’s X3D CPUs—it will depend on the cache’s performance characteristics like bandwidth and latency. That said, the potential for strong gaming performance is there.
Current Arrow Lake CPUs seem to underperform in games for two main reasons. First is the increased memory latency, caused by the memory controller not being on the same chiplet as the CPU cores. They communicate via a “D2D” interface, which apparently suffers from poor performance. A large cache could help significantly here, as its main advantage is shielding the CPU from the negative effects of memory latency (and bandwidth), by handling a large portion of memory accesses itself. X3D Ryzen chips are known to be far less sensitive to slower RAM in games than their non-X3D counterparts.
The second factor is that Arrow Lake has relatively poor L3 cache and ring bus performance. This is likely another side effect of the chiplet design and the performance penalties tied to D2D links. These issues could diminish the benefits of a larger L3 cache—whether it’s part of the main CPU chiplet or a separate SRAM block in another chiplet. In recent years, Intel’s L3 cache has generally lagged behind AMD’s in both latency and bandwidth, and it will need architectural improvements to close that gap. Whether Nova Lake will deliver on that front remains to be seen.
Nova Lake CPUs are expected in the second half of 2026, debuting with the new LGA 1954 socket. They may launch as the Core Ultra 400 series (we assume that the Core Ultra 300 designation will be used by this year’s Panther Lake generation, which will likely only exist for laptops, with the desktop 300 series skipped entirely).
According to leakers, Intel is expected to first release versions with a single CPU chiplet, while dual-chiplet versions with up to 52 cores will follow a quarter later (possibly in Q1 2027 instead of Q4 2026). The gaming CPUs with BLLC—being based on the single-chiplet design—could arrive in the initial wave.
Sources: OneRaichu, Haze, VideoCardz
English translation and edit by Jozef Dudáš
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Intel did a neat trick a long time ago with the i7 5775c, there was some small edram cache and it performed really well.
It was costly but that CPU really blew away other ones in gaming. Still today it can hold against recent ones such as the 7600X: https://hardwareand.co/dossiers/cpu/test-le-cpu-quadcore-core-i7-5775c-revient-du-passe-pour-jouer-en-2024-tient-il-encore-la-route-face-au-ryzen-5-7600x?start=4
I wonder why they abandoned that back then.
Yes, that’s a good observation—thanks for pointing it out. As to why Intel decided to go that route with the 5775C and never continued with it, that’s more a question for our colleague Jan Olšan. 🙂
The reason is probably as you stated, that it was costly.
I have seen suggestions that Intel’s projects involving high-performance integrated GPUs at that time (in Haswell and Skylake processors particularly), which were related development because they relied on the bandwidth of the eDRAM cache, were mostly something that was done for Apple. Those opinions presume that Apple lost interest at some point and that made Intel abandon them. With the eDRAM not being needed for the big iGPUs, perhaps it was not deemed useful anymore. These theories may be giving too much credit or importance to Apple though (the story may have originated as Appla fandom speculation).
It’s possible that it was simply an experiment for Intel – they tried it and it had benefits, but the costs were too much and they weren’t successful enough in bringing them down, so the management killed the project to improve margins. Similar story as 3D XPoint?
One thing that should be kept in mind is the gaming ecosystem at the time. Back then around 2014-2015, it was actually a time when CPU performance was not seen as that important, similarly as fast RAM. Because it was still the norm to game on 60Hz screens, it was around the time 120 Hz and 144 Hz displays were only starting their reign and it wasn’t obvious we are moving towards gaming at much higher frequencies where fast RAM and CPU performance matter again.
In that regard, the big-cache Broadwell chips were too ahead of the time. Their gaming performance was actually appreciated right away and it can truly be said they were the “X3D before X3D”, it just didn’t seem to matter at that time to many. Actually not by that much, perhaps under better circumstances somebody at Intel could have predicted that the “game cache” will matter in next couple years and ensure eDRAM will stay around to be able to be used in later CPUs.
However, it’s also possible that eDRAM would not end up being that useful for later processors and they would have to start anew with SRAM-based cache, anyway. I recall reading something about eDRAM not scaling well to later processes, perhaps it would not really work with good performance on 14nm and Intel 7. But the point is that Intel had opportunity to realize the importance of big cache and make plans accordingly to enable something like BLLC on earlier processors. Perhaps they believed they will be able to lead in gaming anyway because of AMD’s chiplet & lower-clocks handicap. And to be fair, it did work for them for a long time.
“First the Ryzen 7 7800X3D”
Ryzen 7 5800X3D has entered the chat!
I didn’t mention it because at that point AMD was catching up with the superior single-thread performance (and RAM latency) of Alder Lake processors which gained gaming performance crown over the base Zen 3 processors quite decisively and for 5800X3D, it was more like the cache allowed it to catch up rather than become and undisputed leader, IMHO. It was/is hotly debated and depends on what games are used to test, I guess, but it was with 7800X3D where AMD and the X3D processors took clear leadership. That’s where it started to look like the cache is not just an alternative tool to make up for a clock deficit, but something crucial for top gaming performance, period.