Not long ago, we reported on leaked details of AMD’s 2026 or 2027 RDNA 5 graphics cards. YouTuber Moore’s Law is Dead revealed the planned specifications for part of the high-end lineup, back then. Now, new details have surfaced on cheaper GPUs and APUs (processors with integrated graphics) of the lineup. And this is where things get particularly interesting—these lower-cost models might be very different from what we’re used to.
In the previous report, we saw specs for the high-end AT0 GPU and a smaller mainstream AT2 (the letters AT might stand for Alpha Trion according to MLID—these chips are perhaps symbolically no longer labeled as Navi, which covered all RDNA architectures up to RDNA 4). RDNA 5 could mark a major milestone, as it’s expected to unify AMD’s gaming/graphics GPUs with compute-oriented CDNA GPUs (currently based on older GCN designs). Previously, AMD hinted at using the term “UDNA” for them, but it’s unclear whether this name will stick in the end.
AT3 GPU Chiplet
Below the AT2 GPU (which was said to feature ~64 CUs / 4096 shaders and a 192-bit GDDR7 memory interface in the previous leak) comes the AT3 for the lower mainstream tier. It’s expected to feature 48 CUs based on RDNA 5, likely amounting to 3072 shaders (assuming that it’s still 64 shaders per CU in the RDNA 5 architecture).
The unique aspect will be that this GPU will use a different technology instead of graphics memory (GDDR7)—power-efficient mobile LPDDR memory, either LPDDR5X or LPDDR6. This memory operates at lower clock speeds and thus lower bandwidth for a given bus width, but in exchange, it offers a significantly better performance-per-watt ratio. Additionally, the GPU should see greatly improved power efficiency under low or idle loads, making such a GPU potentially well-suited for laptops in terms of battery life during everyday tasks as well as gaming.
The lower memory clock speeds would be compensated for by a wider bus—a 256-bit bus for LPDDR5X, or a 384-bit bus for LPDDR6. It is unclear whether AMD plans to support both memory types. It’s possible that only one of the variants will ultimately be supported, but a decision hasn’t been made yet (or it has been made but this detail hasn’t been part of the documents involved in the leak). LPDDR5X memory is currently available with effective speeds of 8533 to 9600 MHz and could potentially exceed 10 GHz in the future, providing a bandwidth of 320 GB/s (matching today’s Radeon RX 9060 XT). For LPDDR6, effective speeds from 10,667 to 14,400 MHz are expected, which, with a 384-bit bus, would yield a bandwidth of 455 GB/s to 614 GB/s.
Performance will again be aided by a relatively large cache. However, it will not be Infinity Cache in its current form, which is equivalent to L3 cache. In the RDNA 5 architecture, AMD seems to be transitioning to larger L2 cachea that will be faster, though slightly smaller. The AT3 will have 20 MB of it.
An interesting consequence of using LPDDR5X or LPDDR6 would be that AMD would have greater freedom in deciding VRAM capacity. With this bus width, capacities of up to 128 GB should be possible, though consumer gaming graphics cards would likely feature more modest capacities. LPDDR-type chips are commodity technology (widely used as standard RAM in laptops), so they should be cheaper at a given capacity than GDDR-type graphics memory. The use of these memory chips could therefore enable larger VRAM capacities in budget graphics cards.
We don’t have more specs yet, but Moore’s Law is Dead mentions one more detail: the GPU will connect to the system via eight PCI Express lanes—specifically PCI Express 5.0 ×8. This means PCIe 6.0 will not be deployed yet (which wasn’t expected anyway, as PCIe 5.0 was only adopted in graphics cards this year, and for SSDs, PCIe 6.0 is reportedly not arriving until 2030).
AT4
According to Moore’s Law is Dead, an even cheaper, smaller GPU named AT4 is also planned, which will essentially be half of the AT3. This GPU is said to have 24 CUs (1536 shaders), and its L2 cache might also be halved to 10 MB—though this is not yet confirmed. Mobile memory is again expected to be used, but reportedly only LPDDR5X with a 128-bit bus width, this time. The bandwidth would thus be on par with 64-bit GDDR6 memory (160 GB/s). This GPU is also expected to use a PCIe 5.0 ×8 connection.
Both GPUs are reportedly to be manufactured on TSMC’s 3nm process (said to be N3P or N3C—the specific variant is not yet known) and should, according to Moore’s Law is Dead, likely come to market in 2027.
LPDDR-type memories have already been tried in a discrete graphics card. They were used in the Intel Iris Xe (Max) GPU, which were not very successful cards representing an intermediate step between Intel’s integrated GPUs and the first proper discrete Arc cards. Architecturally, they likely drew heavily from iGPUs, and the use of LPDDR4 was probably due to this. The memory controller was most likely inherited from Intel mobile processors.
For the same reasons that speak in favor of its use with GPUs, Nvidia also uses LPDDR memory in the company’s server processors. Furthermore, LPDDR memory over an unusually wide bus is one of the recipes used by Apple’s more powerful processors (Pro, Max, Ultra models) for their high-performance integrated GPUs. This too may be an evidence of their potential suitability for discrete GPUs.
APUs, or Processors with a GPU
It is interesting that this RDNA 5 GPU generation is intended not only for discrete form factors but also as a chiplet—as part of various APUs with the Zen 6 architecture. It is not yet entirely clear how this will be implemented; for instance, whether the processor part will use the memory controller belonging to the GPU, or whether both parts will have their own memory controller with attached memory.
In any case, AMD can address several different products with one chip design and one silicon die being taped-out and manufactured at a foundry. This saves costs on development, design tuning, chip verification, and production ramp-up (where ordering the masks is fairly expensive). Costs are distributed across several products, and the fewer tapeouts a company has to perform, the easier it is to achieve economically viable production. New manufacturing processes are becoming increasingly expensive, not only in terms of unit prices but also in fixed costs for chip development on these technologies. Sharing chiplets across multiple products is therefore likely to become an increasingly common or even necessary strategy.
Medusa Halo
The Zen 6 generation will also include another “Halo” class product, a category introduced this year by the Ryzen AI Max 300 “Strix Halo” processors. This successor is internally codenamed Medusa Halo. According to Moore’s Law is Dead, it is expected to feature a GPU with 48 CUs (3072 shaders), suggesting it could be created by using the AT3 GPU chiplet, as the specifications align. The memory controller is also reportedly the same—supporting either 256-bit LPDDR5X or 384-bit LPDDR6 memory.
The processor is said to contain a base configuration of 12 Zen 6 cores (potentially with some Zen 6c cores) with the option to add another 12 cores via a 2nm CPU die (likely the same that will also be used in other Zen 6 generation processors). Additionally, the IO die is expected to include two Zen 6 LP cores, though this should be taken with a grain of salt for now, as the overall processor design remains unclear. The manufacturing process for the IO die is expected to be N3P.
These processors are expected to use either the FP11 package (likely compatible with motherboards designed for Strix Halo, which also use FP11) or the FP12 package. The first package would probably be intended for use with LPDDR5X memory, while the second would be for LPDDR6 memory.
Medusa Halo Mini
Interestingly, alongside Medusa Halo, AMD is preparing another similarly designed APU with a more powerful GPU but a bit slimmed down. The so-called Medusa Halo Mini is expected to feature a halved GPU with 24 RDNA 5 architecture CUs (so likely 1536 shaders) and 128-bit LPDDR5X memory (it’s not entirely clear if a 192-bit LPDDR6 option exists). This again suggests the possibility that this processor’s “integrated” GPU is actually implemented by incorporating the AT4 chiplet.
The CPU portion is expected to have 12 cores (four Zen 6 cores, eight Zen 6c cores) plus two Zen 6 LP cores in the IO die, bringing the total to 14. In this case, there is likely no option to attach an additional CPU die like with the larger Medusa Halo. The manufacturing process is expected to be TSMC’s 3nm (N3P). A different BGA package, FP10, will be used. Both Medusa Halo versions are reportedly scheduled for release in 2027.
Medusa Point
Medusa Point is intended to be a lower-end, more affordable APU—which, according to Moore’s Law is Dead, would likely serve as a successor to today’s SoC Krackan Point and not necessarily as a successor to the current higher-performance APU Strix Point, as the internal codename might suggest.
Medusa Point is expected to use the FP10 package (meaning it could potentially fit into the same notebook motherboards as the Medusa Halo Mini APU) and is to be composed of a 3nm chip or chiplet die (manufactured using the N3P process). The CPU portion will contain four Zen 6 cores, four Zen 6c cores, and two low-power Zen 6 LP cores. Optionally, a 2nm CPU die with 12 Zen 6 cores can be added.
The integrated graphics of this APU are expected to be located in the IO die (or within the SoC itself if it’s monolithic die?) and will feature 8 CUs (512 shaders). For this processor, it is reportedly unclear whether it will already use the RDNA 5 architecture; some documents allegedly mention only RDNA 3.5 integrated GPU. The processor will support 128-bit LPDDR5X memory but should also be compatible with DDR5.
This is because Medusa Point is reportedly planned to have a desktop version for the AM5 socket. The question, however, is how long it will take to reach the market. The notebook version of Medusa Point (FP10) could arrive by the end of 2026, but it usually takes quite a long time for new APU generations to transition to desktop—often several months to a year.
Source: Moore’s Law is Dead
English translation and edit by Jozef Dudáš
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