Although IBM no longer operates its own fabs, it remains active in semiconductor research. The company announced experimentally produced 2nm chips all the way back in 2021, albeit not manufactured in commercial volume production (which has only now begun at TSMC). IBM is still active in research and has now announced the first chips made on a sub-1 nm node—designated 7A, or 7 angstroms (0.7 nm)—using a new type of transistor.
IBM unveiled an actual experimental chip manufactured using this 0.7nm process. It is apparently composed of various test structures and is certainly not a practical SoC intended for any real-world application. It reportedly contains nearly 100 billion transistors and achieves almost twice the transistor density (exact figures have not been disclosed) of the aforementioned 2nm chip from 2021.
What Are Angstroms / What Does 7 Å Mean?
The angstrom (symbol: Å) is a less commonly used unit of length equal to exactly one tenth of a nanometer. Therefore, 7 Å corresponds to 0.7 nm.
According to IBM, this technology should deliver up to 50% higher performance than its 2nm chip or, alternatively, up to 70% better power efficiency at the same performance level. Once again, it should be emphasized that this is not a manufacturing technology IBM actually uses or is going to use for commercial production, but rather laboratory research that must first be adopted by a manufacturing partner before it can see practical deployment.
IBM manufactured the chip using its research fab operated at its Albany, New York facility. Incidentally, IBM notes that this facility is expected to be equipped with an ASML High-NA EUV lithography system in the future. This implies that the newly announced 0.7nm chip was manufactured without the use of High-NA lithography.
What Is High-NA Technology?
High-NA is an extension of current EUV lithography designed to further improve the ability of extreme ultraviolet light to pattern extremely small structures on semiconductor chips.
It achieves this using anamorphic optics with larger mirrors, increasing the numerical aperture from 0.33 to 0.55, which should enable the fabrication of transistors approximately 1.7 times smaller (a 41% reduction in size). Naturally, implementing this is extremely complex and also comes with disadvantages. This scaling simultaneously halves the exposure area covered by the High-NA EUV system on the wafer. As a result, patterning an entire wafer requires twice as many exposure steps. It will also apparently reduce the maximum possible die size, meaning that, for example, large high-end GPUs will inevitably have to adopt chiplet-based designs.
The New Nanostack Transistor
IBM states that one of the innovations enabling the 0.7nm process used in this experimental chip is the development of a new transistor structure called nanostack. It is said to use nanosheets as the transistor channel, with the nanosheets being only 15 atomic layers thick. Nanosheets have already been employed in GAAFET transistors, which Intel uses in its 1.8nm process (under the RibbonFET name), Samsung in its 3nm and 2nm processes, and TSMC in its 2nm technology. IBM itself also used GAAFET transistors in its experimental 2nm chip introduced in 2021.
Nanostack is intended to be a more advanced implementation, with the improvement lying in the method used to stack the nanosheets on top of one another (they are arranged in horizontal layers within the chip, although this is a characteristic that is already present in GAAFETs). According to IBM, nanostack is unique in enabling staggered channel transistors to be packed more densely through “sequential 3D integration”—something that is critically important for increasing transistor density and thereby improving chip performance and power efficiency, as described by Moore’s Law (although this does not necessarily imply a reduction in cost per transistor, since the cost of manufacturing wafers has been increasing with newer process technologies).
The nanostack structure and the manufacturing process demonstrated by IBM should also make it possible to use different materials in individual nanosheets forming the stacked layers as they are deposited. This could enable performance and power-efficiency optimizations in manufactured chips that were previously impossible.
According to IBM’s research, nanostack transistors could also increase the density of SRAM blocks used on chips for caches, registers, and other on-chip volatile memory structures (such as TLBs, branch predictor memories, and so on). In recent years, a big challenge has been that while new manufacturing processes continue to increase transistor density in logic circuits, allowing those structures to shrink, the desnity of SRAM structures have been scaling much more slowly. Since processors require various caches and other SRAM arrays, this means that the overall die cannot shrink by as much as the new manufacturing process would otherwise allow. As a result, designers are forced to cut features or execution units or economize on cache memory, limiting potential performance gains.
According to IBM, using nanostack in the 0.7nm process could reduce SRAM blocks by as much as 40% compared to the 2nm process, helping to address this problem. The question, of course, is whether that represents a sufficient improvement. We will eventually see how much TSMC manages to reduce SRAM blocks between its own 2nm and 0.7nm process technologies. However, these technologies are unlikely to appear in commercial products before the middle of the next decade. TSMC has not yet announced either a 1nm or a 0.7nm process (although different naming conventions may ultimately be used), and any demonstration of their real capabilities is still a long way off.
Who Could Use This Technology?
IBM itself no longer manufactures advanced chips commercially in its own fabs—they were sold to GlobalFoundries more than a decade ago (the Albany research line was not part of that acquisition). Consequently, IBM’s 2nm and 0.7nm technologies represent research that can only reach practical deployment through other companies licensing the technology. One potential candidate is Japan’s Rapidus, a recently established foundry company seeking to enter the semiconductor industry. Rapidus already collaborates with IBM, so it is possible that it will also license this technology.
- Read more: Japan’s Return to Semiconductor Leaderboards? New Company Developing 2 nm process
- Read more: TSMC’s New Rival in Rapidus? Japanese Company Already out with 2 nm Chips
How successful such licensing could be remains difficult to predict. In the past, when IBM cooperated with Samsung, Motorola/Freescale, and AMD (later GlobalFoundries) on semiconductor process development as part of the Common Platform alliance, there were reportedly issues because IBM’s technologies proved too expensive for economically viable mass production at the other alliance members’ fabs. This illustrates the potential challenges faced by research conducted independently from the economic realities of commercial manufacturing.
In any case, commercialization will probably take just as long—or perhaps even longer—than it did for IBM’s 2nm chip, which was introduced in 2021, while actual 2nm products will only arrive at the end of this year. And those will be chips manufactured by TSMC. (Intel does already have its process marketed as 1.8nm (18A) on the market, but it mostly competes with TSMC’s 3nm technology in terms of its characteristics, so from a technological standpoint it is not really comparable.) The fact that IBM is presenting its results now does not necessarily mean that it has leaped ahead of TSMC’s technological prowess.
Source: IBM
English translation and edit by Jozef Dudáš
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