We’ve already written about the painful measures Intel is implementing get out of the deep red numbers it sunk into due to maintaining and building its own chip fabs (because as a “fabless” player, Intel would be profitable). Among them, however, is one unexpected development: Intel processors are set to reintroduce Hyper-Threading technology for processing multiple threads simultaneously. And this is actually quite peculiar…
Hyper-Threading or HT (Intel’s proprietary branding), or more generally SMT (Simultaneous Multi-Threading), is a technology where a single processor core can handle multiple threads concurrently—typically two, though some IBM Power processors or Sparc chips in the past could manage up to eight. The rationale is that additional threads can make use of processor resources that a single thread might leave idle—for instance, while waiting for memory data. This technique typically improves multi-threaded performance.
HT had been a staple in Intel processors since the Nehalem architecture (the first “Core i” processors in 2008), though it was already tried before in the infamous Pentium 4. Last year, Intel officially abandoned it wit the launch of the Core Ultra 200 mobile processors (Lunar Lake) and later desktop processors (Arrow Lake). Their P-Cores (codenamed Lion Cove) now process only one thread. Intel claimed removing HT (SMT) would shrink die size and improve efficiency by specializing P-Cores purely for single-thread performance. We detailed this in our architecture analysis:
x86 revitalization
Now, in the same statement that announced the cancellation of European and Costa Rican fabs, Intel states it will take steps to halt and reverse its declining market share in PC and server processors—literally to revitalize the “Intel x86 ecosystem.”
Among these revitalization attempts, Lip-Bu Tan mentions reintroducing Hyper-Threading. He cites its removal as a mistake that cost Intel market share and revenue, explicitly stating it created a “competitive disadvantage” and that its return will help “close performance gaps.”
…we are reintroducing simultaneous multi-threading (SMT). Moving away from SMT put us at a competitive disadvantage. Bringing it back will help us close performance gaps.
Notably, these HT remarks (where Tan used the generic “SMT” term—also employed by AMD—rather than Intel’s “HT” branding, by the way) appeared in the context of Xeon server processors. But since these share P-Cores with desktop/mobile Core/Core Ultra chips, the statement might also apply to consumer processors—though this isn’t certain. Many users would welcome HT’s return for improved multi-threading performance, as its absence drew frequent criticism (whether justified or not).
HT removal in servers?
The whole mention of HT’s return doesn’t quite hold up in one respect—and that detail may be more significant than it seems. The idea that Xeon processors for servers were supposed to lose HT (SMT) is not actually something that was previously known; on the contrary no such plan had been made public so far. And when the Lion Cove core used in PC processors removed HT support, Intel engineers and representatives themselves emphasized quite publicly that this is a configurable feature of the core—and they maintained that even though the versions used in Lunar Lake and Arrow Lake chips did not implement this technology, the architecture still accounts for it. Crucially, Intel representatives explicitly stated in interviews that the next generation of server processors derived from this architecture would continue to support HT (SMT).
That next generation comprises the Xeon 7000 “Diamond Rapids” chips (succeeding the current 6th-gen Xeon Scalable “Granite Rapids”). These don’t feature the Lion Cove core directly but instead use a lightly modified derivative—Cougar Cove—manufactured on the 1.8 nm node. Cougar Cove is also set to appear in Core Ultra 300 “Panther Lake” processors for PCs later this year. This core isn’t a true new architecture and is expected to introduce only minor evolutionary updates, you could call it Golden Cove+.
It seems unlikely that Intel would take such a radical step as stripping HT out entirely in this core—a contrast to what it did with Lion Cove. Such a major change would more reasonably be expected with the next P-Core generation that brings a fresh architectural overhaul (what Intel once called Tock in the Tick-Tock scheme). Such shift is set to happen with Coyotte Cove, which is slated to power the next wave of desktop and laptop CPUs in 2026—namely, Core Ultra 400 “Nova Lake”. The next generation of Xeons might be based not quite on this core but on its own tweaked evolution—likely named Griffin Cove—which should appear in PCs as the Core Ultra 500 “Razer Lake” lineup in 2027, but Griffin Cove should still be mostly similar to Coyotte Cove.
There’s a catch, though: Coyotte Cove must already be finalized at this point. Intel would have locked down the architecture some time ago—Nova Lake’s launch is only about a year and a half away, and the design is either undergoing or has already completed tape-out. It is entirely unrealistic to suggest that Hyper-Threading support could now (or in the few months since Lip-Bu Tan took over Intel) be added to the architecture at this stage. While it’s possible in theory that Intel initially planned for the server variant derived from Coyotte Cove to ship without HT, it would only be feasible to reintroduce the feature now if the core had all along been architected with that capability to re-enable HT in mind, from the start.
Which would put it in the same position as Lion Cove—not a reversal in strategy, just a continuation of an existing design. Even in such a scenario, any late-stage decision to re-enable HT would likely delay the processor’s release, unless that decision had been made well in advance (say, several months—more realistically, over a year) before the tape-out stage, which itself happens 12 to 18 months prior to product launch. If HT was never intended to be part of the core, we’d be looking at a delay of at least three years to change course now.
Alternative explanation: HT for small cores?
The entire remark about HT might actually refer to something else. The Intel executive could have been speaking about Xeon processors built with the so-called little cores (E-Cores), which the company recently began producing—namely, the Xeon 6700E and 6900E. Since E-Cores have never supported Hyper-Threading, server CPUs based on them inherently lack this functionality—unlike their P-Core-based counterparts.
It’s possible that these chips underperformed in the market, prompting Intel to discontinue the line. The comment about having “moved away from HT” in server processors might thus refer simply to back.tracking on these E-Core Xeons (even though they were only ever offered as optional alternatives to models with P-Cores and HT, not replacing them) and discontinuing them. Having found them to be a misstep, Intel could now be “returning to HT” in the sense that it will go back to producing only server CPUs with full-fledged P-Cores and Hyper-Threading.
Why wouldn’t Intel say this more directly? Likely because phrasing it this way makes it sound better then admitting a new product line (the E-Core Xeons) was unsuccessful and the investments were wasted, avoiding the appearance of a stark failure.
Hyper-Threading and a unified core
There’s another complication to the HT disappearance-and-return narrative. According to multiple sources, Intel is now aiming to end development of the CPU architecture lineage currently used in large P-Cores—the entire family of “Cove”-named cores. These cores have been designed by Intel’s Israeli team in Haifa, once subject of great acclaim for rescuing Intel from the Pentium 4 era with the tremendously successful Core and Core 2. The same team then went on to produce the architectures of Sandy Bridge, Skylake, and all the following generations of Intel big cores from Sunny Cove in Ice Lake to Lion Cove in Lunar and Arrow Lake.
But that team seems to have lost momentum lately. Their cores have not been delivering performance improvements at the pace the market demands (see the relatively small performance gain in Lion Cove), despite being incredibly complex and occupying substantial die area. AMD, by contrast, appears to be able to match—or even surpass—that level performance (especially considering features like AVX-512) using a much smaller footprint, even now when Intel enjoys a temporary process advantage with 3 nm versus Zen 5’s older 4 nm node. That size disadvantage is even more glaring when compared to the compact designs of ARM cores. In other words, the Cove architecture line now seems burdened with heavy cruft from its long history, and its developers have been unable to sufficiently modernize or streamline it, which undermines its competitiveness.
Haifa vs. Austin
By contrast, Intel’s little/efficient E-Core architectures have seen explosive performance growth in recent years—rapidly catching up to the performance levels of previous generations of large cores developed by the Haifa team. These E-Cores are designed by a team in Austin, Texas, and crucially: they seem capable of delivering an architecture that is power-efficient and die area-efficient. Rumor has it that Intel plans to abandon the original P-Core line and instead let the Austin team handle development of both P-Cores and E-Cores—starting from the current E-Core architecture lineage. Ironically, this resembles that very same pivotal moment in 2006, when Intel dropped its troubled Pentium 4 and replaced it with the Pentium M core—developed by the Israeli team—which immediately catapulted Intel back ahead of then-dominant AMD.
The plan, however, is not to eliminate the distinction between core types, but rather to fork a larger, more powerful core from the E-Core line—with higher IPC and higher clock speeds — to serve as the new P-Core. This strategy is referred to as the “Unified Core” approach. It likely doesn’t signal the end of hybrid CPUs or the P-Core/E-Core distinction (nor does it imply large cores will disappear altogether), but rather that both core types will now stem from a shared architectural foundation. According to some reports—or perhaps educated guesses—this “Unified Core” architecture is expected to debut around 2028 to 2029. It would power CPUs following after Razer Lake (Core Ultra 500) and could potentially be designated Core Ultra 600 (a possible codename has also emerged: “Titan Lake.”
There’s a catch, though: E-Cores today do not support HT, and this technology has never been part of their architecture—with the exception of the original in-order Atom “Bonnell” processors, which aren’t closely related to the newer out-of-order “Mont” core family. Based on this, it appears that the original Unified Core design perhaps didn’t include Hyper-Threading at all. Lip-Bu Tan may now be referring to a decision to retroactively add HT to the Unified Core architecture—either to the P-Core variant only, or potentially even to both P- and E-Core derivatives.
A more pessimistic scenario would be that—due to the lack of HT—Intel has abandoned the plan to transition to the new unified architecture altogether. Instead, the company may choose to let the Israeli team continue refining the increasingly inefficient “Cove” big cores, despite their disproportionately large die footprint. That would be an unfortunate decision, since smaller cores make it easier to fit more of them on a chip—that itself can offset the lack of HT by sheer quantity of cores. At present, the CPU team in Austin seems significantly more capable, and it would likely benefit Intel to move forward with adopting their unified design—so hopefully, Lip-Bu Tan doesn’t make that kind of mistake.
What it actually meant remains to be seen…
At this point, all we can do is wait for more information to clarify what this announcement really signals about the turmoil and internal shifts at Intel. Hopefully it leads to welcome—rather than unwelcome—surprises.
It’s also possible that the reintroduction of HT isn’t a major course correction by the new leadership, but simply a case of “wagging the dog”—much ado about nothing. Lip-Bu Tan may have just needed a clear, digestible example of his actions to show investors, who likely lack deep intuition about how processor development and the surrounding business ecosystem actually work. Hyper-Threading makes for a convenient illustration: it shows the company is making changes, correcting past missteps (which implies future progress), and responding to market demands. Even if, in reality, the overall strategy remains unchanged.
The truth is, Intel’s “competitive disadvantage” seen today isn’t simply caused by the absence of HT—and bringing it back alone won’t fix the situation (though it may help improve performance to some degree). But much like voters in democratic countries, stock investors tend to respond to simple narratives and promises of easy solutions. They don’t always recognize that the underlying problems are far more complex—and that magical simple fixes able to resolve them usually don’t exist.
Source: Intel
English translation and edit by Jozef Dudáš
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